Documentation ¶
Overview ¶
Package mos65xx implements MOS Technology 65xx CPU emulation.
Index ¶
- Constants
- Variables
- func FetchWord(mem memory.Memory, addr uint16) uint16
- func FetchWordBug(mem memory.Memory, addr uint16) uint16
- func StoreWord(mem memory.Memory, addr, value uint16)
- type AddressMode
- type CPU
- type Instruction
- type InstructionPrinter
- type Interrupt
- type Mnemonic
- type Model
- type Monitor
- type Registers
Constants ¶
const ( NMIVector = 0xfffa ResetVector = 0xfffc IRQVector = 0xfffe )
Vectors
const ( C uint8 = 1 << iota // Carry flag, 1 = true Z // Zero, 1 = Result zero I // IRQ disable, 1 = disable D // Decimal mode, 1 = true B // BRK command U // Unused V // Overflow, 1 = true N // Negative, 1 = true )
Processor status register flags
const ( Hz = 1 KHz = 1000 * Hz MHz = 1000 * KHz )
Frequency scale
const ( // FormatDefault resembles neskell's output format FormatDefault = `` /* 126-byte string literal not displayed */ // FormatNintendulator resembles nintendulator's output format FormatNintendulator = `{{printf "%04X %-9s %s %-27s A:%02X X:%02X Y:%02X P:%02X SP:%02x" .PC .RawX .Mnemonic .Operand .A .X .Y .P .S}}` )
Instruction formats
Variables ¶
var ( MOS6502 = Model{ Name: "MOS Technology 6502", Frequency: 1 * MHz, ExternalMemory: 0x10000, HasBCD: true, HasIRQ: true, HasNMI: true, } MOS6503 = Model{ Name: "MOS Technology 6503", Frequency: 1 * MHz, ExternalMemory: 0x1000, HasBCD: true, HasIRQ: true, HasNMI: true, } MOS6504 = Model{ Name: "MOS Technology 6504", Frequency: 1 * MHz, ExternalMemory: 0x2000, HasBCD: true, HasIRQ: true, } MOS6505 = Model{ Name: "MOS Technology 6505", Frequency: 1 * MHz, ExternalMemory: 0x1000, HasBCD: true, HasIRQ: true, HasReady: true, } MOS6506 = Model{ Name: "MOS Technology 6506", Frequency: 1 * MHz, ExternalMemory: 0x1000, HasBCD: true, HasIRQ: true, } MOS6507 = Model{ Name: "MOS Technology 6507", Frequency: 1 * MHz, ExternalMemory: 0x2000, } MOS6510 = Model{ Name: "MOS Technology 6510", Frequency: 1.023 * MHz, ExternalMemory: 0x10000, HasBCD: true, HasNMI: true, HasReady: true, } MOS6510T = Model{ Name: "MOS Technology 6510T", Frequency: 1.023 * MHz, ExternalMemory: 0x10000, HasBCD: true, } MOS7501 = Model{ Name: "MOS Technology 7501", Frequency: 1.023 * MHz, ExternalMemory: 0x10000, HasBCD: true, HasReady: true, } MOS8501 = Model{ Name: "MOS Technology 8501", Frequency: 1.023 * MHz, ExternalMemory: 0x10000, HasBCD: true, HasReady: true, } MOS8502 = Model{ Name: "MOS Technology 8502", Frequency: 2 * MHz, ExternalMemory: 0x10000, HasBCD: true, HasNMI: true, HasReady: true, } // Ricoh2A03 is the 8-bit microprocessor in the Nintendo Entertainment System (NTSC version) Ricoh2A03 = Model{ Name: "Ricoh 2A03", Frequency: 1 * MHz, ExternalMemory: 0x10000, HasIRQ: true, HasNMI: true, } // Ricoh2A07 is the 8-bit microprocessor in the Nintendo Entertainment System (PAL version) Ricoh2A07 = Model{ Name: "Ricoh 2A07", Frequency: 1 * MHz, ExternalMemory: 0x10000, HasIRQ: true, HasNMI: true, } )
Models
var ( // InstructionFormat is the default instruction format InstructionFormat = FormatDefault )
Functions ¶
func FetchWordBug ¶
FetchWordBug is a helper to fetch a 16-bit word from memory
Types ¶
type AddressMode ¶
type AddressMode uint8
AddressMode determines how the CPU will fetch the address
const ( Implied AddressMode = iota Accumulator Immediate ZeroPage ZeroPageX ZeroPageY Relative Absolute AbsoluteX AbsoluteY Indirect IndexedIndirect IndirectIndexed )
Address modes
func (AddressMode) Cycles ¶
func (mode AddressMode) Cycles() int
Cycles to fetch the operand address
func (AddressMode) FetchPenalty ¶
func (mode AddressMode) FetchPenalty() int
FetchPenalty is the cycle penalty for doing page cross or branch on a fetch operation.
func (AddressMode) StorePenalty ¶
func (mode AddressMode) StorePenalty() int
StorePenalty is the cycle penalty for doing page cross on a store operation.
func (AddressMode) String ¶
func (mode AddressMode) String() string
type CPU ¶
type CPU interface { // Memory as observed by the CPU memory.Memory // Registers returns a pointer to the CPU registers Registers() *Registers // IRQ requests an interrupt IRQ() // NMI requests an non-maskable interrupt NMI() // Reset requests a cold reset Reset() // Ready Ready(bool) // Step fetches and executes the next instruction, returning the total // number of cycles spent on performing the operation. Step() int // Run until the CPU receives a HLT instruction, returning the total // number of cycles spent. Run() int // Halted returns true if the CPU received a HLT instruction Halted() bool // Attach a monitor Attach(Monitor) }
CPU represents a MOS Technology 65xx Central Processing Unit
type Instruction ¶
type Instruction struct { // CPU this instruction is executed on CPU CPU // Cycles elapsed Cycles int // Mnemonic is the current operation Mnemonic // Registers state for instruction Registers // AddressMode is the addressing mode for this instruction AddressMode // Raw opcode and address bytes Raw []byte }
Instruction describes an instruction that's about to be executed
func (Instruction) Addr ¶
func (in Instruction) Addr() (addr uint16)
Addr is the operand address for the current instruction.
type InstructionPrinter ¶
type InstructionPrinter func(string)
InstructionPrinter will output a formatted string before execution.
func (InstructionPrinter) BeforeExecute ¶
func (m InstructionPrinter) BeforeExecute(cpu CPU, in Instruction) bool
BeforeExecute triggers the printer function.
type Mnemonic ¶
type Mnemonic uint8
Mnemonic is an instruction
const ( ADC Mnemonic = iota AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA HLT LAX SAX DCP ISC RLA RRA SLO SRE ANC ALR ARR XAA AHX TAS SHX SHY LAS AXS )
mnemonics
type Model ¶
type Model struct { Name string Frequency float64 // Typical clock frequency in Hz ExternalMemory int // External addressable memory size InternalMemory int // Internal RAM size HasBCD bool // Decimal mode support HasIRQ bool // IRQ support HasNMI bool // NMI support HasReady bool // RDY support }
Model of the MOS Technology 65xx (or compatible) CPU
type Monitor ¶
type Monitor interface { // BeforeExecute gets called before instruction execution, returning false // will stop execution and halt the CPU. BeforeExecute(CPU, Instruction) bool }
Monitor for the CPU monitors instruction executions