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v0.31.1 Latest Latest
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 Go to latest Published: Jul 1, 2020 License: BSD-3-Clause Imports: 3 Imported by: 0

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Index

Constants

View Source 
const (
	EQ = Cond(0x0) // equal to
	NE = Cond(0x1) // not equal to
	CS = Cond(0x2) // carry set
	CC = Cond(0x3) // carry clear
	MI = Cond(0x4) // minus, negative
	PL = Cond(0x5) // positive or zero
	VS = Cond(0x6) // signed overflow
	VC = Cond(0x7) // no signed overflow
	HI = Cond(0x8) // greater than (unsigned)
	LS = Cond(0x9) // less than or equal to (unsigned)
	GE = Cond(0xa) // greater than or equal to (signed)
	LT = Cond(0xb) // less than (signed)
	GT = Cond(0xc) // greater than (signed)
	LE = Cond(0xd) // less than or equal to (signed)

	HS = CS // greater than or equal to (unsigned)
	LO = CC // less than (unsigned)
)
View Source 
const (
	Unscaled = S(0 << 12)
	Scaled   = S(1 << 12)
)
View Source 
const (
	LSL = Shift(0 << 22)
	LSR = Shift(1 << 22)
	ASR = Shift(2 << 22)
)
View Source 
const (
	UXTB = Ext(0 << 13)
	UXTH = Ext(1 << 13)
	UXTW = Ext(2 << 13)
	UXTX = Ext(3 << 13)
	SXTB = Ext(4 << 13)
	SXTH = Ext(5 << 13)
	SXTW = Ext(6 << 13)
	SXTX = Ext(7 << 13)
)
View Source 
const (
	// Compare & branch (immediate)
	CBZ  = RegImm19Size(0x1a<<25 | 0<<24)
	CBNZ = RegImm19Size(0x1a<<25 | 1<<24)

	// Conditional branch (immediate)
	Bc = CondImm19(0x2a<<25 | 0<<24 | 0<<4)

	// Exception generation
	BRK = Imm16(0xd4<<24 | 1<<21 | 0<<2 | 0<<0)

	// Test & branch (immediate)
	TBZ  = RegImm14Bit(0x1b<<25 | 0<<24)
	TBNZ = RegImm14Bit(0x1b<<25 | 1<<24)

	// Unconditional branch (immediate)
	B  = Imm26(0<<31 | 5<<26)
	BL = Imm26(1<<31 | 5<<26)

	// Unconditional branch (register)
	BR  = Reg(0x6b<<25 | 0<<21 | 0x1f<<16 | 0<<10 | 0<<0)
	BLR = Reg(0x6b<<25 | 1<<21 | 0x1f<<16 | 0<<10 | 0<<0)
	RET = Reg(0x6b<<25 | 2<<21 | 0x1f<<16 | 0<<10 | 0<<0)

	// Load/store register (immediate post-indexed)
	LDRpost = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 1<<22 | 0<<21 | 1<<10)

	// Load/store register (immediate pre-indexed)
	STRpre = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 0<<22 | 0<<21 | 3<<10)

	// Load/store register (register offset)
	LDRr = RegRegSOptionRegSize(1<<31 | 7<<27 | 0<<24 | 1<<22 | 1<<21 | 2<<10)

	// Load/store register (unscaled immediate)
	STUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 0<<22 | 0<<21 | 0<<10)
	LDUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 1<<22 | 0<<21 | 0<<10)

	// Load/store register (unsigned immediate)
	STR = RegRegImm12Size(1<<31 | 7<<27 | 1<<24 | 0<<22)
	LDR = RegRegImm12Size(1<<31 | 7<<27 | 1<<24 | 1<<22)

	// Add/subtract (immediate)
	ADDi  = RegRegImm12ShiftSf(0<<30 | 0<<29 | 0x11<<24)
	ADDSi = RegRegImm12ShiftSf(0<<30 | 1<<29 | 0x11<<24)
	SUBi  = RegRegImm12ShiftSf(1<<30 | 0<<29 | 0x11<<24)
	SUBSi = RegRegImm12ShiftSf(1<<30 | 1<<29 | 0x11<<24)

	// Bitfield
	UBFM = RegRegImm6Imm6NSf(2<<29 | 0x26<<23 | 0<<22)

	// Move wide (immediate)
	MOVN = RegImm16HwSf(0<<29 | 0x25<<23)
	MOVZ = RegImm16HwSf(2<<29 | 0x25<<23)
	MOVK = RegImm16HwSf(3<<29 | 0x25<<23)

	// Address generation
	ADR = RegImm19Imm2(0<<31 | 0x10<<24)

	// Add/subtract (extended register)
	ADDe  = RegRegImm3ExtRegSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<22 | 1<<21)
	SUBSe = RegRegImm3ExtRegSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<22 | 1<<21)

	// Add/subtract (shifted register)
	ADDs  = RegRegImm6RegShiftSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<21)
	SUBs  = RegRegImm6RegShiftSf(1<<30 | 0<<29 | 0x0b<<24 | 0<<21)
	SUBSs = RegRegImm6RegShiftSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<21)

	// Conditional select
	CSEL  = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 0<<10)
	CSINC = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 1<<10)

	// Logical (shifted register)
	ANDs  = RegRegImm6RegShiftSf(0<<29 | 0x0a<<24 | 0<<21)
	ORRs  = RegRegImm6RegShiftSf(1<<29 | 0x0a<<24 | 0<<21)
	ANDSs = RegRegImm6RegShiftSf(3<<29 | 0x0a<<24 | 0<<21)

	// Variable shift
	RORV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x0b<<10)

	// Bit operations
	RBIT = RegRegSf(1<<30 | 0<<29 | 0xd6<<21 | 0<<16 | 0<<10)
	CLZ  = RegRegSf(1<<30 | 0<<29 | 0xd6<<21 | 0<<16 | 4<<10)

	// Multiply
	MADD = RegRegRegRegSf(0<<29 | 0x1b<<24 | 0<<21 | 0<<15)
	MSUB = RegRegRegRegSf(0<<29 | 0x1b<<24 | 0<<21 | 1<<15)

	// Divide
	UDIV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x02<<10)
	SDIV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x03<<10)

	// Floating-point move (register)
	FMOV = RegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<17 | 0<<15 | 0x10<<10)

	// Floating-point move (general) - size arguments must be identical
	FMOVtog   = RegRegTypeSf(0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<19 | 6<<16 | 0<<10)
	FMOVfromg = RegRegTypeSf(0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<19 | 7<<16 | 0<<10)

	// Floating-point arithmetic (1 source)
	FNEG = RegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<17 | 2<<15 | 0x10<<10)

	// Floating-point comparison
	FCMP = DiscardRegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<14 | 8<<10 | 0<<3 | 0<<0)

	// Floating-point conditional select
	FCSEL = RegRegCondRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 3<<10)

	// System register
	MSR_FPSR = SystemReg(0x354<<22 | 0<<21 | 1<<20 | 0xda21<<5)
	MRS_FPSR = SystemReg(0x354<<22 | 1<<21 | 1<<20 | 0xda21<<5)
)
View Source 
const (
	AddsubAdd = Addsub(0)
	AddsubSub = Addsub(1)
)
View Source 
const (
	LogicAnd = Logic(0)
	LogicOrr = Logic(1)
	LogicEor = Logic(2)
)
View Source 
const (
	ExtendS = Bitfield(0)
	ExtendU = Bitfield(2)
)
View Source 
const (
	DivisionUnsigned = DataProcessing2(0x2)
	DivisionSigned   = DataProcessing2(0x3)

	VariableShiftL  = DataProcessing2(0x8)
	VariableShiftLR = DataProcessing2(0x9)
	VariableShiftAR = DataProcessing2(0xa)
	VariableShiftRR = DataProcessing2(0xb)
)
View Source 
const (
	//                            17     15
	UnaryFloatAbs     = UnaryFloat(0<<2 | 1<<0)
	UnaryFloatNeg     = UnaryFloat(0<<2 | 2<<0)
	UnaryFloatSqrt    = UnaryFloat(0<<2 | 3<<0)
	UnaryFloatCvtTo32 = UnaryFloat(1<<2 | 0<<0)
	UnaryFloatCvtTo64 = UnaryFloat(1<<2 | 1<<0)

	//                             18     15
	UnaryFloatRIntN = UnaryFloat(1<<3 | 0<<0)
	UnaryFloatRIntP = UnaryFloat(1<<3 | 1<<0)
	UnaryFloatRIntM = UnaryFloat(1<<3 | 2<<0)
	UnaryFloatRIntZ = UnaryFloat(1<<3 | 3<<0)
)
View Source 
const (
	//                             13     12     10
	BinaryFloatAdd = BinaryFloat(1<<3 | 0<<2 | 2<<0)
	BinaryFloatSub = BinaryFloat(1<<3 | 1<<2 | 2<<0)

	//                             15     12     10
	BinaryFloatMul = BinaryFloat(0<<5 | 0<<2 | 2<<0)
	BinaryFloatDiv = BinaryFloat(1<<2 | 2<<0)

	//                             14     12     10
	BinaryFloatMax = BinaryFloat(1<<4 | 0<<2 | 2<<0)
	BinaryFloatMin = BinaryFloat(1<<4 | 1<<2 | 2<<0)
)
View Source 
const (
	//                                   19     16
	ConvertIntS      = ConvertCategory(0<<3 | 2<<0) // SCVTF
	ConvertIntU      = ConvertCategory(0<<3 | 3<<0) // UCVTF
	ReinterpretFloat = ConvertCategory(0<<3 | 6<<0) // FMOV
	ReinterpretInt   = ConvertCategory(0<<3 | 7<<0) // FMOV
	TruncFloatS      = ConvertCategory(3<<3 | 0<<0) // FCVTZS
	TruncFloatU      = ConvertCategory(3<<3 | 1<<0) // FCVTZU
)
View Source 
const (
	//                   30      27      26     22
	StoreB   = Memory(0<<14 | 7<<11 | 0<<10 | 0<<6)
	LoadB    = Memory(0<<14 | 7<<11 | 0<<10 | 1<<6)
	LoadSB64 = Memory(0<<14 | 7<<11 | 0<<10 | 2<<6)
	LoadSB32 = Memory(0<<14 | 7<<11 | 0<<10 | 3<<6)
	StoreH   = Memory(1<<14 | 7<<11 | 0<<10 | 0<<6)
	LoadH    = Memory(1<<14 | 7<<11 | 0<<10 | 1<<6)
	LoadSH64 = Memory(1<<14 | 7<<11 | 0<<10 | 2<<6)
	LoadSH32 = Memory(1<<14 | 7<<11 | 0<<10 | 3<<6)
	StoreW   = Memory(2<<14 | 7<<11 | 0<<10 | 0<<6)
	LoadW    = Memory(2<<14 | 7<<11 | 0<<10 | 1<<6)
	LoadSW64 = Memory(2<<14 | 7<<11 | 0<<10 | 2<<6)
	StoreF32 = Memory(2<<14 | 7<<11 | 1<<10 | 0<<6)
	LoadF32  = Memory(2<<14 | 7<<11 | 1<<10 | 1<<6)
	StoreD   = Memory(3<<14 | 7<<11 | 0<<10 | 0<<6)
	LoadD    = Memory(3<<14 | 7<<11 | 0<<10 | 1<<6)
	StoreF64 = Memory(3<<14 | 7<<11 | 1<<10 | 0<<6)
	LoadF64  = Memory(3<<14 | 7<<11 | 1<<10 | 1<<6)
)
View Source 
const (
	RegFakeSP = reg.R(29)
)

Variables

This section is empty.

Functions

func Int14 

func Int14(i int32) uint32

func Int19 

func Int19(i int32) uint32

func Int26 

func Int26(i int32) uint32

func Int9 

func Int9(i int32) uint32

func LogicalShiftLeft added in v0.20.0 

func LogicalShiftLeft(rd, rn reg.R, uimm uint32, t wa.Size) uint32

func PopReg added in v0.25.0 

func PopReg(r reg.R, t wa.Type) uint32

func PushReg added in v0.25.0 

func PushReg(r reg.R, t wa.Type) uint32

func Uint12 

func Uint12(i uint64) uint32

func Uint16 

func Uint16(i uint64) uint32

Types

type Addsub 

type Addsub uint8

Add/subtract instruction's "op" field

func (Addsub) OpcodeImm 

func (op Addsub) OpcodeImm() RegRegImm12ShiftSf

func (Addsub) OpcodeRegExt 

func (op Addsub) OpcodeRegExt() RegRegImm3ExtRegSf

type BinaryFloat added in v0.25.0 

type BinaryFloat uint8

Floating-point (2 source) instruction's bits 10-15

func (BinaryFloat) OpcodeReg added in v0.25.0 

func (op BinaryFloat) OpcodeReg() RegRegRegType

type Bitfield added in v0.20.0 

type Bitfield uint8

Bitfield instruction’s "opc" field

func (Bitfield) Opcode added in v0.20.0 

func (op Bitfield) Opcode() RegRegImm6Imm6NSf

type Cond 

type Cond uint32

type CondImm19 

type CondImm19 uint32

func (CondImm19) CondI19 

func (op CondImm19) CondI19(cond Cond, imm uint32) uint32

type ConvertCategory added in v0.25.0 

type ConvertCategory uint8

Floating-point/integer instruction's "rmode" and "opcode" fields

func (ConvertCategory) Opcode added in v0.25.0 

func (op ConvertCategory) Opcode() RegRegTypeSf

type DataProcessing2 added in v0.20.0 

type DataProcessing2 uint8

Data-processing (2 source) instruction's "opcode" field

func (DataProcessing2) OpcodeReg added in v0.20.0 

func (op DataProcessing2) OpcodeReg() RegRegRegSf

type DiscardRegRegType added in v0.25.0 

type DiscardRegRegType uint32

func (DiscardRegRegType) RnRm added in v0.25.0 

func (op DiscardRegRegType) RnRm(rn, rm reg.R, t wa.Size) uint32

type Ext 

type Ext uint32

func SizeSignExt 

func SizeSignExt(t wa.Size) Ext

func SizeZeroExt 

func SizeZeroExt(t wa.Size) Ext

type Imm16 

type Imm16 uint32

func (Imm16) I16 

func (op Imm16) I16(imm uint32) uint32

type Imm26 

type Imm26 uint32

func (Imm26) I26 

func (op Imm26) I26(imm uint32) uint32

type Logic 

type Logic uint8

Logical instruction's "opc" field

func (Logic) OpcodeImm 

func (op Logic) OpcodeImm() RegRegImm6Imm6NSf

func (Logic) OpcodeReg 

func (op Logic) OpcodeReg() RegRegImm6RegShiftSf

type Memory 

type Memory uint16

Load/store instruction's most significant half-word excluding bit 24 (and 21)

func (Memory) OpcodeReg added in v0.20.0 

func (op Memory) OpcodeReg() RegRegSOptionReg

func (Memory) OpcodeUnscaled 

func (op Memory) OpcodeUnscaled() RegRegImm9

type Reg 

type Reg uint32

func (Reg) Rn 

func (op Reg) Rn(rn reg.R) uint32

type RegImm14Bit 

type RegImm14Bit uint32

func (RegImm14Bit) RtI14Bit 

func (op RegImm14Bit) RtI14Bit(rt reg.R, imm, bit uint32) uint32

type RegImm16HwSf 

type RegImm16HwSf uint32

func (RegImm16HwSf) RdI16Hw 

func (op RegImm16HwSf) RdI16Hw(rd reg.R, imm, hw uint32, t wa.Size) uint32

type RegImm19Imm2 

type RegImm19Imm2 uint32

func (RegImm19Imm2) RdI19hiI2lo 

func (op RegImm19Imm2) RdI19hiI2lo(r reg.R, hi, lo uint32) uint32

type RegImm19Size 

type RegImm19Size uint32

func (RegImm19Size) RtI19 

func (op RegImm19Size) RtI19(r reg.R, imm uint32, t wa.Size) uint32

type RegRegCondRegSf 

type RegRegCondRegSf uint32

func (RegRegCondRegSf) RdRnCondRm 

func (op RegRegCondRegSf) RdRnCondRm(rd, rn reg.R, cond Cond, rm reg.R, t wa.Size) uint32

type RegRegCondRegType added in v0.25.0 

type RegRegCondRegType uint32

func (RegRegCondRegType) RdRnCondRm added in v0.25.0 

func (op RegRegCondRegType) RdRnCondRm(rd, rn reg.R, cond Cond, rm reg.R, t wa.Size) uint32

type RegRegImm12ShiftSf 

type RegRegImm12ShiftSf uint32

func (RegRegImm12ShiftSf) RdRnI12S2 

func (op RegRegImm12ShiftSf) RdRnI12S2(rd, rn reg.R, imm, shift uint32, t wa.Size) uint32

type RegRegImm12Size 

type RegRegImm12Size uint32

func (RegRegImm12Size) RdRnI12 

func (op RegRegImm12Size) RdRnI12(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegImm3ExtRegSf 

type RegRegImm3ExtRegSf uint32

func (RegRegImm3ExtRegSf) RdRnI3ExtRm 

func (op RegRegImm3ExtRegSf) RdRnI3ExtRm(rd, rn reg.R, imm uint32, option Ext, rm reg.R, t wa.Size) uint32

type RegRegImm6Imm6NSf 

type RegRegImm6Imm6NSf uint32

func (RegRegImm6Imm6NSf) RdRnI6sI6r 

func (op RegRegImm6Imm6NSf) RdRnI6sI6r(rd, rn reg.R, imms, immr uint32, t wa.Size) uint32

type RegRegImm6RegShiftSf 

type RegRegImm6RegShiftSf uint32

func (RegRegImm6RegShiftSf) RdRnI6RmS2 

func (op RegRegImm6RegShiftSf) RdRnI6RmS2(rd, rn reg.R, imm uint32, rm reg.R, shift Shift, t wa.Size) uint32

type RegRegImm9 

type RegRegImm9 uint32

func (RegRegImm9) RtRnI9 

func (op RegRegImm9) RtRnI9(rt, rn reg.R, imm uint32) uint32

type RegRegImm9Size 

type RegRegImm9Size uint32

func (RegRegImm9Size) RtRnI9 

func (op RegRegImm9Size) RtRnI9(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegRegRegSf added in v0.20.0 

type RegRegRegRegSf uint32

func (RegRegRegRegSf) RdRnRaRm added in v0.20.0 

func (op RegRegRegRegSf) RdRnRaRm(rd, rn, ra, rm reg.R, t wa.Size) uint32

type RegRegRegSf added in v0.20.0 

type RegRegRegSf uint32

func (RegRegRegSf) RdRnRm added in v0.20.0 

func (op RegRegRegSf) RdRnRm(rd, rn, rm reg.R, t wa.Size) uint32

type RegRegRegType added in v0.25.0 

type RegRegRegType uint32

func (RegRegRegType) RdRnRm added in v0.25.0 

func (op RegRegRegType) RdRnRm(rd, rn, rm reg.R, t wa.Size) uint32

type RegRegSOptionReg added in v0.20.0 

type RegRegSOptionReg uint32

func (RegRegSOptionReg) RtRnSOptionRm added in v0.20.0 

func (op RegRegSOptionReg) RtRnSOptionRm(rt, rn reg.R, s S, option Ext, rm reg.R) uint32

type RegRegSOptionRegSize 

type RegRegSOptionRegSize uint32

func (RegRegSOptionRegSize) RtRnSOptionRm 

func (op RegRegSOptionRegSize) RtRnSOptionRm(rt, rn reg.R, s S, option Ext, rm reg.R, t wa.Type) uint32

type RegRegSf added in v0.20.0 

type RegRegSf uint32

func (RegRegSf) RdRn added in v0.20.0 

func (op RegRegSf) RdRn(rd, rn reg.R, t wa.Size) uint32

type RegRegType added in v0.25.0 

type RegRegType uint32

func (RegRegType) RdRn added in v0.25.0 

func (op RegRegType) RdRn(rd, rn reg.R, t wa.Size) uint32

type RegRegTypeSf added in v0.25.0 

type RegRegTypeSf uint32

func (RegRegTypeSf) RdRn added in v0.25.0 

func (op RegRegTypeSf) RdRn(rd, rn reg.R, floatType, intType wa.Size) uint32

type S added in v0.20.0 

type S uint32

type Shift added in v0.20.0 

type Shift uint32

type SystemReg added in v0.31.0 

type SystemReg uint32

func (SystemReg) Rt added in v0.31.0 

func (op SystemReg) Rt(rt reg.R) uint32

type UnaryFloat added in v0.25.0 

type UnaryFloat uint8

Floating-point (1 source) instruction's bits 15-20

func (UnaryFloat) Opcode added in v0.25.0 

func (op UnaryFloat) Opcode() RegRegType

Source Files

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