Documentation
¶
Index ¶
- func GNUSyntax(inst Inst) string
- func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string
- type AddrMode
- type Arg
- type Args
- type Arrangement
- type Cond
- type ExtShift
- type Imm
- type Imm64
- type ImmShift
- type Imm_c
- type Imm_clrex
- type Imm_dcps
- type Imm_fp
- type Imm_hint
- type Imm_option
- type Imm_prfop
- type Inst
- type MemExtend
- type MemImmediate
- type Op
- type PCRel
- type Pstatefield
- type Reg
- type RegExtshiftAmount
- type RegSP
- type RegisterWithArrangement
- type RegisterWithArrangementAndIndex
- type Systemreg
Constants ¶
This section is empty.
Variables ¶
This section is empty.
Functions ¶
func GNUSyntax ¶
GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the ARM Reference Manual.
func GoSyntax ¶
GoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0. The reader text should read from the text segment using text addresses as offsets; it is used to display pc-relative loads as constant loads.
Types ¶
type AddrMode ¶
type AddrMode uint8
An AddrMode is an ARM addressing mode.
const ( AddrPostIndex AddrMode // [R], X - use address R, set R = R + X AddrPreIndex // [R, X]! - use address R + X, set R = R + X AddrOffset // [R, X] - use address R + X AddrPostReg // [Rn], Rm - - use address Rn, set Rn = Rn + Rm )
type Arg ¶
type Arg interface {
String() string
// contains filtered or unexported methods
}
An Arg is a single instruction argument, one of these types: Reg, RegSP, ImmShift, RegExtshiftAmount, PCRel, MemImmediate, MemExtend, Imm, Imm64, Imm_hint, Imm_clrex, Imm_dcps, Cond, Imm_c, Imm_option, Imm_prfop, Pstatefield, Systemreg, Imm_fp RegisterWithArrangement, RegisterWithArrangementAndIndex.
type Args ¶
type Args [5]Arg
An Args holds the instruction arguments. If an instruction has fewer than 5 arguments, the final elements in the array are nil.
type Arrangement ¶
type Arrangement uint8
const ( ArrangementB Arrangement Arrangement8B Arrangement16B ArrangementH Arrangement4H Arrangement8H ArrangementS Arrangement2S Arrangement4S ArrangementD Arrangement1D Arrangement2D Arrangement1Q )
func (Arrangement) String ¶
func (a Arrangement) String() (result string)
type Imm_fp ¶
type Imm_fp struct {
// contains filtered or unexported fields
}
An Imm_fp is a signed floating-point constant.
type Imm_option ¶
type Imm_option uint8
An Imm_option is an integer constant for DMB/DSB/ISB instruction.
func (Imm_option) String ¶
func (i Imm_option) String() string
type Inst ¶
type Inst struct {
Op Op // Opcode mnemonic
Enc uint32 // Raw encoding bits.
Args Args // Instruction arguments, in ARM manual order.
}
An Inst is a single instruction.
type MemExtend ¶
type MemExtend struct {
Base RegSP
Index Reg
Extend ExtShift
// Amount indicates the index shift amount (but also see ShiftMustBeZero field below).
Amount uint8
// Refer to ARM reference manual, for byte load/store(register), the index
// shift amount must be 0, encoded in "S" as 0 if omitted, or as 1 if present.
// a.ShiftMustBeZero is set true indicates the index shift amount must be 0.
// In GNU syntax, a #0 shift amount is printed if Amount is 1 but ShiftMustBeZero
// is true; #0 is not printed if Amount is 0 and ShiftMustBeZero is true.
// Both cases represent shift by 0 bit.
ShiftMustBeZero bool
}
A MemExtend is a memory reference made up of a base R and index expression X. The effective memory address is R or R+X depending on Index, Extend and Amount.
type MemImmediate ¶
A MemImmediate is a memory reference made up of a base R and immediate X. The effective memory address is R or R+X depending on AddrMode.
func (MemImmediate) String ¶
func (m MemImmediate) String() string
type Op ¶
type Op uint16
An Op is an ARM64 opcode.
const ( ABS Op ADC ADCS ADD ADDHN ADDHN2 ADDP ADDS ADDV ADR ADRP AESD AESE AESIMC AESMC AND ANDS ASR ASRV AT B BFI BFM BFXIL BIC BICS BIF BIT BL BLR BR BRK BSL CBNZ CBZ CCMN CCMP CINC CINV CLREX CLS CLZ CMEQ CMGE CMGT CMHI CMHS CMLE CMLT CMN CMP CMTST CNEG CNT CRC32B CRC32CB CRC32CH CRC32CW CRC32CX CRC32H CRC32W CRC32X CSEL CSET CSETM CSINC CSINV CSNEG DC DCPS1 DCPS2 DCPS3 DMB DRPS DSB DUP EON EOR ERET EXT EXTR FABD FABS FACGE FACGT FADD FADDP FCCMP FCCMPE FCMEQ FCMGE FCMGT FCMLE FCMLT FCMP FCMPE FCSEL FCVT FCVTAS FCVTAU FCVTL FCVTL2 FCVTMS FCVTMU FCVTN FCVTN2 FCVTNS FCVTNU FCVTPS FCVTPU FCVTXN FCVTXN2 FCVTZS FCVTZU FDIV FMADD FMAX FMAXNM FMAXNMP FMAXNMV FMAXP FMAXV FMIN FMINNM FMINNMP FMINNMV FMINP FMINV FMLA FMLS FMOV FMSUB FMUL FMULX FNEG FNMADD FNMSUB FNMUL FRECPE FRECPS FRECPX FRINTA FRINTI FRINTM FRINTN FRINTP FRINTX FRINTZ FRSQRTE FRSQRTS FSQRT FSUB HINT HLT HVC IC INS ISB LD1 LD1R LD2 LD2R LD3 LD3R LD4 LD4R LDAR LDARB LDARH LDAXP LDAXR LDAXRB LDAXRH LDNP LDP LDPSW LDR LDRB LDRH LDRSB LDRSH LDRSW LDTR LDTRB LDTRH LDTRSB LDTRSH LDTRSW LDUR LDURB LDURH LDURSB LDURSH LDURSW LDXP LDXR LDXRB LDXRH LSL LSLV LSR LSRV MADD MLA MLS MNEG MOV MOVI MOVK MOVN MOVZ MRS MSR MSUB MUL MVN MVNI NEG NEGS NGC NGCS NOP NOT ORN ORR PMUL PMULL PMULL2 PRFM PRFUM RADDHN RADDHN2 RBIT RET REV REV16 REV32 REV64 ROR RORV RSHRN RSHRN2 RSUBHN RSUBHN2 SABA SABAL SABAL2 SABD SABDL SABDL2 SADALP SADDL SADDL2 SADDLP SADDLV SADDW SADDW2 SBC SBCS SBFIZ SBFM SBFX SCVTF SDIV SEV SEVL SHA1C SHA1H SHA1M SHA1P SHA1SU0 SHA1SU1 SHA256H SHA256H2 SHA256SU0 SHA256SU1 SHADD SHL SHLL SHLL2 SHRN SHRN2 SHSUB SLI SMADDL SMAX SMAXP SMAXV SMC SMIN SMINP SMINV SMLAL SMLAL2 SMLSL SMLSL2 SMNEGL SMOV SMSUBL SMULH SMULL SMULL2 SQABS SQADD SQDMLAL SQDMLAL2 SQDMLSL SQDMLSL2 SQDMULH SQDMULL SQDMULL2 SQNEG SQRDMULH SQRSHL SQRSHRN SQRSHRN2 SQRSHRUN SQRSHRUN2 SQSHL SQSHLU SQSHRN SQSHRN2 SQSHRUN SQSHRUN2 SQSUB SQXTN SQXTN2 SQXTUN SQXTUN2 SRHADD SRI SRSHL SRSHR SRSRA SSHL SSHLL SSHLL2 SSHR SSRA SSUBL SSUBL2 SSUBW SSUBW2 ST1 ST2 ST3 ST4 STLR STLRB STLRH STLXP STLXR STLXRB STLXRH STNP STP STR STRB STRH STTR STTRB STTRH STUR STURB STURH STXP STXR STXRB STXRH SUB SUBHN SUBHN2 SUBS SUQADD SVC SXTB SXTH SXTL SXTL2 SXTW SYS SYSL TBL TBNZ TBX TBZ TLBI TRN1 TRN2 TST UABA UABAL UABAL2 UABD UABDL UABDL2 UADALP UADDL UADDL2 UADDLP UADDLV UADDW UADDW2 UBFIZ UBFM UBFX UCVTF UDIV UHADD UHSUB UMADDL UMAX UMAXP UMAXV UMIN UMINP UMINV UMLAL UMLAL2 UMLSL UMLSL2 UMNEGL UMOV UMSUBL UMULH UMULL UMULL2 UQADD UQRSHL UQRSHRN UQRSHRN2 UQSHL UQSHRN UQSHRN2 UQSUB UQXTN UQXTN2 URECPE URHADD URSHL URSHR URSQRTE URSRA USHL USHLL USHLL2 USHR USQADD USRA USUBL USUBL2 USUBW USUBW2 UXTB UXTH UXTL UXTL2 UZP1 UZP2 WFE WFI XTN XTN2 YIELD ZIP1 ZIP2 )
type PCRel ¶
type PCRel int64
A PCRel describes a memory address (usually a code label) as a distance relative to the program counter.
type Pstatefield ¶
type Pstatefield uint8
const ( SPSel Pstatefield = iota DAIFSet DAIFClr )
func (Pstatefield) String ¶
func (p Pstatefield) String() string
type Reg ¶
type Reg uint16
A Reg is a single register. The zero value denotes W0, not the absence of a register.
const ( W0 Reg = iota W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 WZR X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 XZR B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 WSP = WZR // These are different registers with the same encoding. SP = XZR // These are different registers with the same encoding. )
type RegExtshiftAmount ¶
type RegExtshiftAmount struct {
// contains filtered or unexported fields
}
func (RegExtshiftAmount) String ¶
func (rea RegExtshiftAmount) String() string
type RegisterWithArrangement ¶
type RegisterWithArrangement struct {
// contains filtered or unexported fields
}
Register with arrangement: <Vd>.<T>, { <Vt>.8B, <Vt2>.8B},
func (RegisterWithArrangement) String ¶
func (r RegisterWithArrangement) String() string
type RegisterWithArrangementAndIndex ¶
type RegisterWithArrangementAndIndex struct {
// contains filtered or unexported fields
}
Register with arrangement and index:
<Vm>.<Ts>[<index>],
{ <Vt>.B, <Vt2>.B }[<index>].
func (RegisterWithArrangementAndIndex) String ¶
func (r RegisterWithArrangementAndIndex) String() string
Source Files