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Published: Dec 10, 2022 License: BSD-3-Clause Imports: 4 Imported by: 0

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Constants

View Source
const (
	RegResult     = reg.Result
	RegScratch    = reg.ScratchISA
	RegZero       = reg.R(2)
	RegStackLimit = reg.R(3)
	RegStack      = reg.R(4)
	RegMemoryBase = reg.R(14)
	RegTextBase   = reg.R(15)
)
View Source
const (
	BaseScratch = BaseReg(RegScratch)
	BaseZero    = BaseReg(RegZero)
	BaseMemory  = BaseReg(RegMemoryBase)
	BaseText    = BaseReg(RegTextBase)
)
View Source
const (
	// GP opcodes
	ADD     = RM(0x03)
	OR      = RM(0x0b)
	AND     = RM(0x23)
	SUB     = RM(0x2b)
	XOR     = RM(0x33)
	CMP     = RM(0x3b)
	CMOVB   = RM2(0x0f<<8 | 0x42)
	CMOVAE  = RM2(0x0f<<8 | 0x43)
	CMOVE   = RM2(0x0f<<8 | 0x44)
	CMOVNE  = RM2(0x0f<<8 | 0x45)
	CMOVBE  = RM2(0x0f<<8 | 0x46)
	CMOVA   = RM2(0x0f<<8 | 0x47)
	CMOVS   = RM2(0x0f<<8 | 0x48)
	CMOVP   = RM2(0x0f<<8 | 0x4a)
	CMOVL   = RM2(0x0f<<8 | 0x4c)
	CMOVGE  = RM2(0x0f<<8 | 0x4d)
	CMOVLE  = RM2(0x0f<<8 | 0x4e)
	CMOVG   = RM2(0x0f<<8 | 0x4f)
	PUSHo   = O(0x50)
	POPo    = O(0x58)
	MOVSXD  = RM(0x63) // I64 only
	PUSHi   = Ipush(0x6a)
	IMULi   = RMI(0x6b)
	JNOcb   = Db(0x71)
	JBcb    = Db(0x72)
	JAEcb   = Db(0x73)
	JEcb    = Db(0x74)
	JNEcb   = Db(0x75)
	JBEcb   = Db(0x76)
	JAcb    = Db(0x77)
	JScb    = Db(0x78)
	JPcb    = Db(0x7a)
	JLcb    = Db(0x7c)
	JGEcb   = Db(0x7d)
	JLEcb   = Db(0x7e)
	JGcb    = Db(0x7f)
	ADDi    = MI(0x81<<16 | 0x83<<8 | 0<<opcodeBase)
	ORi     = MI(0x81<<16 | 0x83<<8 | 1<<opcodeBase)
	ANDi    = MI(0x81<<16 | 0x83<<8 | 4<<opcodeBase)
	SUBi    = MI(0x81<<16 | 0x83<<8 | 5<<opcodeBase)
	XORi    = MI(0x81<<16 | 0x83<<8 | 6<<opcodeBase)
	CMPi    = MI(0x81<<16 | 0x83<<8 | 7<<opcodeBase)
	TEST8   = RMdata8(0x84) // MR opcode
	TEST    = RM(0x85)      // MR opcode
	MOV8mr  = RMdata8(0x88)
	MOV16mr = RMdata16(0x89)
	MOVmr   = RM(0x89) // RegReg is untested
	MOV     = RM(0x8b)
	LEA     = RM(0x8d)
	POP     = M(0x8f<<8 | 0<<opcodeBase)
	JBcd    = D2d(0x0f<<8 | 0x82)
	JAEcd   = D2d(0x0f<<8 | 0x83)
	JEcd    = D2d(0x0f<<8 | 0x84)
	JNEcd   = D2d(0x0f<<8 | 0x85)
	JBEcd   = D2d(0x0f<<8 | 0x86)
	JAcd    = D2d(0x0f<<8 | 0x87)
	JScd    = D2d(0x0f<<8 | 0x88)
	JPcd    = D2d(0x0f<<8 | 0x8a)
	JLcd    = D2d(0x0f<<8 | 0x8c)
	JGEcd   = D2d(0x0f<<8 | 0x8d)
	JLEcd   = D2d(0x0f<<8 | 0x8e)
	JGcd    = D2d(0x0f<<8 | 0x8f)
	PAUSE   = NPprefix(0x90)
	SETB    = Mex2(0x0f<<8 | 0x92)
	SETAE   = Mex2(0x0f<<8 | 0x93)
	SETE    = Mex2(0x0f<<8 | 0x94)
	SETNE   = Mex2(0x0f<<8 | 0x95)
	SETBE   = Mex2(0x0f<<8 | 0x96)
	SETA    = Mex2(0x0f<<8 | 0x97)
	SETS    = Mex2(0x0f<<8 | 0x98)
	SETP    = Mex2(0x0f<<8 | 0x9a)
	SETL    = Mex2(0x0f<<8 | 0x9c)
	SETGE   = Mex2(0x0f<<8 | 0x9d)
	SETLE   = Mex2(0x0f<<8 | 0x9e)
	SETG    = Mex2(0x0f<<8 | 0x9f)
	CDQ     = NP(0x99)
	IMUL    = RM2(0x0f<<8 | 0xaf)
	MOVZX8  = RM2(0x0f<<8 | 0xb6) // RegReg is untested
	MOVZX16 = RM2(0x0f<<8 | 0xb7) // RegReg is untested
	MOV64i  = OI(0xb8)
	POPCNT  = RMprefix(0xf3<<8 | 0xb8)
	TZCNT   = RMprefix(0xf3<<8 | 0xbc)
	LZCNT   = RMprefix(0xf3<<8 | 0xbd)
	BSF     = RM2(0x0f<<8 | 0xbc)
	BSR     = RM2(0x0f<<8 | 0xbd)
	MOVSX8  = RM2(0x0f<<8 | 0xbe) // RegReg is untested
	MOVSX16 = RM2(0x0f<<8 | 0xbf) // RegReg is untested
	ROLi    = MI(0xc1<<8 | 0<<opcodeBase)
	RORi    = MI(0xc1<<8 | 1<<opcodeBase)
	SHLi    = MI(0xc1<<8 | 4<<opcodeBase)
	SHRi    = MI(0xc1<<8 | 5<<opcodeBase)
	SARi    = MI(0xc1<<8 | 7<<opcodeBase)
	RET     = NP(0xc3)
	MOV8i   = MI8(0xc6<<8 | 0<<opcodeBase)
	MOV16i  = MI16(0xc7<<8 | 0<<opcodeBase)
	MOV32i  = MI32(0xc7<<8 | 0<<opcodeBase)
	MOVi    = MI(0xc7<<16 | 0<<opcodeBase)
	ROL     = M(0xd3<<8 | 0<<opcodeBase)
	ROR     = M(0xd3<<8 | 1<<opcodeBase)
	SHL     = M(0xd3<<8 | 4<<opcodeBase)
	SHR     = M(0xd3<<8 | 5<<opcodeBase)
	SAR     = M(0xd3<<8 | 7<<opcodeBase)
	LOOPcb  = Db(0xe2)
	CALLcd  = Dd(0xe8)
	JMPcd   = Dd(0xe9)
	JMPcb   = Db(0xeb)
	NEG     = M(0xf7<<8 | 3<<opcodeBase)
	DIV     = M(0xf7<<8 | 6<<opcodeBase)
	IDIV    = M(0xf7<<8 | 7<<opcodeBase)
	INC     = M(0xff<<8 | 0<<opcodeBase)
	DEC     = M(0xff<<8 | 1<<opcodeBase)
	PUSH    = M(0xff<<8 | 6<<opcodeBase)

	// GP opcode pairs
	JEc  = D12(JEcd)<<16 | D12(JEcb)
	JPc  = D12(JPcd)<<16 | D12(JPcb)
	JLEc = D12(JLEcd)<<16 | D12(JLEcb)

	// GP/SSE opcodes
	CVTSI2Sx  = RMscalar(0x2a)           // CVTSI2SS or CVTSI2SD
	CVTTSx2SI = RMscalar(0x2c)           // CVTTSS2SI or CVTTSD2SI
	MOVx      = RMprefix(0x66<<8 | 0x6e) // MOVD or MOVQ
	MOVxmr    = RMprefix(0x66<<8 | 0x7e) // register parameters reversed

	// SSE opcodes
	MOVSx   = RMscalar(0x10)  // MOVSS or MOVSD
	MOVSxmr = RMscalar(0x11)  // RegReg is redundant
	MOVAPx  = RMpacked(0x28)  // MOVAPS or MOVAPD
	UCOMISx = RMpacked(0x2e)  // UCOMISS or UCOMISD
	ROUNDSx = RMIscalar(0x3a) // ROUNDSS or ROUNDSD
	SQRTSx  = RMscalar(0x51)  // SQRTSS or SQRTSD
	ANDPx   = RMpacked(0x54)  // ANDPS or ANDPD
	ORPx    = RMpacked(0x56)  // ORPS or ORPD
	XORPx   = RMpacked(0x57)  // XORPS or XORPD
	ADDSx   = RMscalar(0x58)  // ADDSS or ADDSD
	MULSx   = RMscalar(0x59)  // MULSS or MULSD
	CVTS2Sx = RMscalar(0x5a)  // CVTS2SS or CVTS2SD
	SUBSx   = RMscalar(0x5c)  // SUBSS or SUBSD
	MINSx   = RMscalar(0x5d)  // MINSS or MINSD
	DIVSx   = RMscalar(0x5e)  // DIVSS or DIVSD
	MAXSx   = RMscalar(0x5f)  // MAXSS or MAXSD
	PXOR    = RMprefix(0x66<<8 | 0xef)
)
View Source
const (
	InsnAdd = ALInsn(0 << opcodeBase)
	InsnOr  = ALInsn(1 << opcodeBase)
	InsnAnd = ALInsn(4 << opcodeBase)
	InsnSub = ALInsn(5 << opcodeBase)
	InsnXor = ALInsn(6 << opcodeBase)
)
View Source
const (
	InsnRotl = ShiftInsn(0 << opcodeBase)
	InsnRotr = ShiftInsn(1 << opcodeBase)
	InsnShl  = ShiftInsn(4 << opcodeBase)
	InsnShrU = ShiftInsn(5 << opcodeBase)
	InsnShrS = ShiftInsn(7 << opcodeBase)
)
View Source
const (
	InsnLtU = CCInsn(0x2)
	InsnGeU = CCInsn(0x3)
	InsnEq  = CCInsn(0x4)
	InsnNe  = CCInsn(0x5)
	InsnLeU = CCInsn(0x6)
	InsnGtU = CCInsn(0x7)
	InsnLtS = CCInsn(0xc)
	InsnGeS = CCInsn(0xd)
	InsnLeS = CCInsn(0xe)
	InsnGtS = CCInsn(0xf)
)
View Source
const (
	ModMem       = Mod(0)
	ModMemDisp8  = Mod(64)
	ModMemDisp32 = Mod(128)
	ModReg       = Mod(192)
)
View Source
const (
	Rex  = byte(64)
	RexW = rexWRXB(8) // 64-bit operand size
	RexR = rexWRXB(4) // extension of the ModR/M reg field
	RexX = rexWRXB(2) // extension of the SIB index field
	RexB = rexWRXB(1) // extension of the ModR/M r/m field, SIB base field, or Opcode reg field
)
View Source
const (
	// Immediate values for ROUNDSSD
	RoundModeNearest = 0x0
	RoundModeFloor   = 0x1
	RoundModeCeil    = 0x2
	RoundModeTrunc   = 0x3
)
View Source
const (
	Scale0 = Scale(0 << 6)
	Scale1 = Scale(1 << 6)
	Scale2 = Scale(2 << 6)
	Scale3 = Scale(3 << 6)
)
View Source
const (
	ModRMSIB = ModRM(4)
)
View Source
const (
	OneSize = wa.Type(0) // for instructions which don't use RexW
)
View Source
const (
	RexMemory = RexB // RegMemoryBase >= 8
)

Variables

This section is empty.

Functions

This section is empty.

Types

type ALInsn

type ALInsn byte

func (ALInsn) Opcode

func (op ALInsn) Opcode() RM

func (ALInsn) OpcodeI

func (ro ALInsn) OpcodeI() MI

type Base

type Base byte

type BaseReg

type BaseReg reg.R

type CCInsn

type CCInsn byte

func (CCInsn) CmovccOpcode

func (nib CCInsn) CmovccOpcode() RM2

func (CCInsn) JccOpcodeC

func (cc CCInsn) JccOpcodeC() D12

func (CCInsn) JccOpcodeCb

func (nib CCInsn) JccOpcodeCb() Db

func (CCInsn) JccOpcodeCd

func (nib CCInsn) JccOpcodeCd() D2d

func (CCInsn) SetccOpcode

func (nib CCInsn) SetccOpcode() Mex2

type D12

type D12 uint32 // combination

func (D12) Addr

func (ops D12) Addr(text *code.Buf, addr int32) (far bool)

func (D12) AddrStub

func (ops D12) AddrStub(text *code.Buf) int32

func (D12) Stub

func (ops D12) Stub(text *code.Buf, near bool) int32

type D2d

type D2d uint16 // two opcode bytes

func (D2d) Addr32

func (op D2d) Addr32(text *code.Buf, addr int32)

func (D2d) Size

func (D2d) Size() int8

func (D2d) Stub32

func (op D2d) Stub32(text *code.Buf) int32

type Db

type Db byte // opcode byte

func (Db) Addr8

func (op Db) Addr8(text *code.Buf, addr int32)

func (Db) Rel8

func (op Db) Rel8(text *code.Buf, disp int8)

func (Db) Size

func (Db) Size() int8

func (Db) Stub8

func (op Db) Stub8(text *code.Buf) int32

type Dd

type Dd byte // opcode byte

func (Dd) Addr32

func (op Dd) Addr32(text *code.Buf, addr int32)

func (Dd) MissingFunction

func (op Dd) MissingFunction(text *code.Buf, align bool)

func (Dd) Size

func (Dd) Size() int8

func (Dd) Stub32

func (op Dd) Stub32(text *code.Buf) int32

type Index

type Index byte

type Ipush

type Ipush byte // opcode of instruction variant with 8-bit immediate

func (Ipush) Imm

func (op Ipush) Imm(text *code.Buf, val int32)

type M

type M uint16 // opcode byte and ModRO byte

func (M) Reg

func (op M) Reg(text *code.Buf, t wa.Type, r reg.R)

type MI

type MI uint32 // opcode bytes for 32-bit value and 8-bit value; and common ModRO byte

func (MI) RegImm

func (ops MI) RegImm(text *code.Buf, t wa.Type, r reg.R, val int32)

func (MI) RegImm32

func (op MI) RegImm32(text *code.Buf, t wa.Type, r reg.R, val int32)

func (MI) RegImm8

func (op MI) RegImm8(text *code.Buf, t wa.Type, r reg.R, val int8)

func (MI) StackDispImm32

func (op MI) StackDispImm32(text *code.Buf, t wa.Type, disp, val int32)

func (MI) StackImm8

func (op MI) StackImm8(text *code.Buf, t wa.Type, val int8)

type MI16

type MI16 uint16 // opcode byte and ModRO byte

func (MI16) MemDispImm

func (op MI16) MemDispImm(text *code.Buf, _ wa.Type, base BaseReg, disp int32, val16 int64)

MemDispImm ignores the type argument.

type MI32

type MI32 uint16 // opcode byte and ModRO byte

func (MI32) MemDispImm

func (op MI32) MemDispImm(text *code.Buf, t wa.Type, base BaseReg, disp int32, val32 int64)

type MI8

type MI8 uint16 // opcode byte and ModRO byte

func (MI8) MemDispImm

func (op MI8) MemDispImm(text *code.Buf, _ wa.Type, base BaseReg, disp int32, val8 int64)

MemDispImm ignores the type argument.

type Mex2

type Mex2 uint16 // two opcode bytes

func (Mex2) OneSizeReg

func (op Mex2) OneSizeReg(text *code.Buf, r reg.R)

type Mod

type Mod byte

type ModRM

type ModRM byte

type ModRO

type ModRO byte

type NP

type NP byte

func (NP) Simple

func (op NP) Simple(text *code.Buf)

func (NP) Type

func (op NP) Type(text *code.Buf, t wa.Type)

type NPprefix

type NPprefix byte

func (NPprefix) Simple

func (op NPprefix) Simple(text *code.Buf)

type O

type O byte

func (O) RegResult

func (op O) RegResult(text *code.Buf)

func (O) RegScratch

func (op O) RegScratch(text *code.Buf)

func (O) RegZero

func (op O) RegZero(text *code.Buf)

type OI

type OI byte

func (OI) RegImm64

func (op OI) RegImm64(text *code.Buf, r reg.R, val int64)

type RM

type RM byte // opcode byte

func (RM) RegMemDisp

func (op RM) RegMemDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, disp int32)

func (RM) RegMemIndexDisp

func (op RM) RegMemIndexDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, index reg.R, s Scale, disp int32)

func (RM) RegReg

func (op RM) RegReg(text *code.Buf, t wa.Type, r, r2 reg.R)

func (RM) RegStackDisp

func (op RM) RegStackDisp(text *code.Buf, t wa.Type, r reg.R, disp int32)

func (RM) RegStackDisp8

func (op RM) RegStackDisp8(text *code.Buf, t wa.Type, r reg.R, disp int8)

func (RM) RegStackStub32

func (op RM) RegStackStub32(text *code.Buf, t wa.Type, r reg.R) int32

type RM2

type RM2 uint16 // two opcode bytes

func (RM2) RegMemDisp

func (op RM2) RegMemDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, disp int32)

func (RM2) RegReg

func (op RM2) RegReg(text *code.Buf, t wa.Type, r, r2 reg.R)

func (RM2) RegStack

func (op RM2) RegStack(text *code.Buf, t wa.Type, r reg.R)

func (RM2) RegStackDisp

func (op RM2) RegStackDisp(text *code.Buf, t wa.Type, r reg.R, disp int32)

type RMI

type RMI byte // opcode of 8-bit variant, transformed to 32-bit variant automatically

func (RMI) RegRegImm

func (op RMI) RegRegImm(text *code.Buf, t wa.Type, r, r2 reg.R, val int32)

type RMIscalar

type RMIscalar byte // opcode of 8-bit variant, transformed to 32-bit variant automatically

func (RMIscalar) RegRegImm8

func (op RMIscalar) RegRegImm8(text *code.Buf, t wa.Type, r, r2 reg.R, val int8)

type RMdata16

type RMdata16 byte // opcode byte

func (RMdata16) RegMemDisp

func (op RMdata16) RegMemDisp(text *code.Buf, _ wa.Type, r reg.R, base BaseReg, disp int32)

type RMdata8

type RMdata8 byte // opcode byte

func (RMdata8) RegMemDisp

func (op RMdata8) RegMemDisp(text *code.Buf, _ wa.Type, r reg.R, base BaseReg, disp int32)

func (RMdata8) RegRegStackLimit

func (op RMdata8) RegRegStackLimit(text *code.Buf)

type RMpacked

type RMpacked byte // second opcode byte; type-dependent variable-length prefix

func (RMpacked) RegMemDisp

func (op RMpacked) RegMemDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, disp int32)

func (RMpacked) RegReg

func (op RMpacked) RegReg(text *code.Buf, t wa.Type, r, r2 reg.R)

type RMprefix

type RMprefix uint16 // fixed-length prefix and second opcode byte

func (RMprefix) RegMemDisp

func (op RMprefix) RegMemDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, disp int32)

func (RMprefix) RegReg

func (op RMprefix) RegReg(text *code.Buf, t wa.Type, r, r2 reg.R)

func (RMprefix) RegStack

func (op RMprefix) RegStack(text *code.Buf, t wa.Type, r reg.R)

func (RMprefix) RegStackDisp

func (op RMprefix) RegStackDisp(text *code.Buf, t wa.Type, r reg.R, disp int32)

type RMscalar

type RMscalar byte // second opcode byte; type-dependent fixed-length prefix

func (RMscalar) RegMemDisp

func (op RMscalar) RegMemDisp(text *code.Buf, t wa.Type, r reg.R, base BaseReg, disp int32)

func (RMscalar) RegReg

func (op RMscalar) RegReg(text *code.Buf, t wa.Type, r, r2 reg.R)

func (RMscalar) TypeRegReg

func (op RMscalar) TypeRegReg(text *code.Buf, floatType, intType wa.Type, r, r2 reg.R)

type Scale

type Scale byte

func TypeScale

func TypeScale(t wa.Type) Scale

type ShiftInsn

type ShiftInsn byte

func (ShiftInsn) Opcode

func (ro ShiftInsn) Opcode() M

func (ShiftInsn) OpcodeI

func (ro ShiftInsn) OpcodeI() MI

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