cxl

package
v1.3.2 Latest Latest
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 Go to latest Published: Apr 15, 2024 License: Apache-2.0 Imports: 18 Imported by: 0

Documentation

Overview

This file implements the CXL Mailbox related structures and methods based on CXL spec rev3.0

This file implements the API functions of the cxl library

Index

Constants

View Source 
const (
	CDAT_DSMAS_Struct_Handle   = iota // 0 Device Scoped Memory Affinity Structure (DSMAS)
	CDAT_DSLBIS_Struct_Handle         // 1 Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
	CDAT_DSMSCIS_Struct_Handle        // 2 Device Scoped Memory Side Cache Information Structure (DSMSCIS)
	CDAT_DSIS_Struct_Handle           // 3 Device Scoped Initiator Structure (DSIS)
	CDAT_DSEMTS_Struct_Handle         // 4 Device Scoped EFI Memory Type Structure (DSEMTS)
	CDAT_SSLBIS_Struct_Handle         // 5 Switch Scoped Latency and Bandwidth Information Structure (SSLBIS)
)

// CDAT entry type to data struct

View Source 
const (
	ACPI_CEDT_CXL_HOST_BRIDGE                         cedt_struct_types = iota // 0
	ACPI_CEDT_CXL_FIXED_MEMORY_WINDOW                                          // 1
	ACPI_CEDT_CXL_XOR_INTERLEAVE_MATH                                          // 2
	ACPI_CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRCUT                          // 3
)
View Source 
const (
	CXL_DVSEC_PCIE_DVSEC_FOR_CXL           cxl_dvsec_id = iota // 0
	CXL_DVSEC_UNDEFINED_ID1                                    // 1
	CXL_DVSEC_NON_CXL_FUNC_MAP                                 // 2
	CXL_DVSEC_CXL2_0_EXR_DVESC                                 // 3
	CXL_DVSEC_GPF_DVSEC_FOR_PORTS                              // 4
	CXL_DVSEC_GPF_DVSEC_FOR_DEV                                // 5
	CXL_DVSEC_UNDEFINED_ID6                                    // 6
	CXL_DVSEC_PCIE_DVSEC_FOR_FLEX_BUS_PORT                     // 7
	CXL_DVSEC_REGISTER_LOCATOR                                 // 8
	CXL_DVSEC_MLD                                              // 9
	CXL_DVSEC_PCIE_DVSEC_FOR_TEST_CAP                          // a
)
View Source 
const (
	CXL_CMPREG_NULL                     cxl_cmp_cap_id = iota // 0
	CXL_CMPREG_CAP                                            // 1
	CXL_CMPREG_RAS_CAP                                        // 2
	CXL_CMPREG_SECURE_CAP                                     // 3
	CXL_CMPREG_LINK_CAP                                       // 4
	CXL_CMPREG_HDM_DECODER_CAP                                // 5
	CXL_CMPREG_EXT_SECURE_CAP                                 // 6
	CXL_CMPREG_IDE_CAP                                        // 7
	CXL_CMPREG_SNOOP_FLT_CAP                                  // 8
	CXL_CMPREG_TIMEOUT_N_ISOLATION_CAP                        // 9
	CXL_CMPREG_CACEHMEM_EXT_CAP                               // A
	CXL_CMPREG_BI_ROUTE_TABLE_CAP                             // B
	CXL_CMPREG_BI_DECODER_CAP                                 // C
	CXL_CMPREG_CACHE_ID_ROUTE_TABLE_CAP                       // D
	CXL_CMPREG_CACHE_ID_DECODER_CAP                           // E
	CXL_CMPREG_EXT_HDM_DECODER_CAP                            // F
)
View Source 
const (
	CXL_MEMDEV_STATUS            = 1
	CXL_MEMDEV_PRIMARY_MAILBOX   = 2
	CXL_MEMDEV_SECONDARY_MAILBOX = 3
	CXL_MEMDEV_MEMDEV_STATUS     = 0x4000
)
View Source 
const (
	DBG_LVL_DEFAUILT    = iota //0
	DBG_LVL_BASIC              //1
	DBG_LVL_INFO               //2
	DBG_LVL_DETAIL             //3
	DBG_LVL_DEEP_DETAIL        //4
)
View Source 
const CXL_DOE_PROTOCOL_TABLE_ACCESS = 2

////// DOE CDAT structure

View Source 
const CXL_Vendor_ID = 0x1E98
View Source 
const DOE_PCIE_ext_cap_ID = 0x2E
View Source 
const EXT_DVSEC_OFFSET = 0x100
View Source 
const MB_CHECK_INTERVAL = 100 // Millisecond
View Source 
const MB_DOORBELL_CHECK_INTERVAL = 100 // Millisecond
View Source 
const MB_DOORBELL_TIMEOUT = 5000 // Millisecond
View Source 
const MB_READ_INTERVAL = 10 // Millisecond
View Source 
const MB_WRITE_INTERVAL = 10 // Millisecond

Variables

View Source 
var (
	DOE_CAPABILITIES_Interrupt_Support        = u32field{/* contains filtered or unexported fields */}
	DOE_CAPABILITIES_Interrupt_Message_Number = u32field{/* contains filtered or unexported fields */}
	DOE_CONTROL_Abort                         = u32field{/* contains filtered or unexported fields */}
	DOE_CONTROL_Interrupt_Enable              = u32field{/* contains filtered or unexported fields */}
	DOE_CONTROL_Go                            = u32field{/* contains filtered or unexported fields */}
	DOE_STATUS_Busy                           = u32field{/* contains filtered or unexported fields */}
	DOE_STATUS_Interrupt_Status               = u32field{/* contains filtered or unexported fields */}
	DOE_STATUS_Interrupt_Error                = u32field{/* contains filtered or unexported fields */}
	DOE_STATUS_Object_Ready                   = u32field{/* contains filtered or unexported fields */}
)
View Source 
var (
	MAILBOX_CAPABILITIES_REGISTER_PAYLOAD_SIZE                                  = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CAPABILITIES_REGISTER_MB_DOORBELL_INTERRUPT_CAPABLE                 = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CAPABILITIES_REGISTER_BACKGROUND_COMMAND_COMPLETE_INTERRUPT_CAPABLE = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CAPABILITIES_REGISTER_INTERRUPT_MESSAGE_NUMBER                      = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CAPABILITIES_REGISTER_MAILBOX_READY_TIME                            = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CAPABILITIES_REGISTER_TYPE                                          = u32field{/* contains filtered or unexported fields */}

	MAILBOX_CONTROL_REGISTER_DOORBELL                              = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CONTROL_REGISTER_DOORBELL_INTERRUPT                    = u32field{/* contains filtered or unexported fields */}
	MAILBOX_CONTROL_REGISTER_BACKGROUND_COMMAND_COMPLETE_INTERRUPT = u32field{/* contains filtered or unexported fields */}

	MAILBOX_COMMAND_REGISTER_COMMAND_OPCODE = u64field{/* contains filtered or unexported fields */}
	MAILBOX_COMMAND_REGISTER_PAYLOAD_LENGTH = u64field{/* contains filtered or unexported fields */}

	MAILBOX_STATUS_REGISTER_BACKGROUND_OPERATION            = u64field{/* contains filtered or unexported fields */}
	MAILBOX_STATUS_REGISTER_RETURN_CODE                     = u64field{/* contains filtered or unexported fields */}
	MAILBOX_STATUS_REGISTER_VENDOR_SPECIFIC_EXTENDED_STATUS = u64field{/* contains filtered or unexported fields */}

	BACKGROUND_COMMAND_STATUS_REGISTER_COMMAND_OPCODE                  = u64field{/* contains filtered or unexported fields */}
	BACKGROUND_COMMAND_STATUS_REGISTER_PERCENTAGE_COMPLETE             = u64field{/* contains filtered or unexported fields */}
	BACKGROUND_COMMAND_STATUS_REGISTER_RETURN_CODE                     = u64field{/* contains filtered or unexported fields */}
	BACKGROUND_COMMAND_STATUS_REGISTER_VENDOR_SPECIFIC_EXTENDED_STATUS = u64field{/* contains filtered or unexported fields */}
)
View Source 
var ACPITables = ACPI{}

ACPI tables are static, initialize via init() func

View Source 
var CXL_FW_PACK_SIZE = 128
View Source 
var DSLBIS_data_string = [...]string{
	"DSLBIS Access Latency: %d ps\n",
	"DSLBIS Read Latency: %d ps\n",
	"DSLBIS Write Latency: %d ps\n",
	"DSLBIS Access Bandwidth: %d MB/s\n",
	"DSLBIS Read Bandwidth: %d MB/s\n",
	"DSLBIS Write Bandwidth: %d MB/s\n"}
View Source 
var MB_ReturnCode = [23]string{
	"Success",
	"Background Command Started",
	"Invalid Input",
	"Unsupported",
	"Internal Error",
	"Retry Required",
	"Busy",
	"Media Disabled",
	"FW Transfer in Progress",
	"FW Transfer Out of Order",
	"FW Authentication Failed",
	"Invalid Slot",
	"Activation Failed, FW Rolled Back",
	"Activation Failed, Cold Reset Required",
	"Invalid Handle",
	"Invalid Physical Address",
	"Inject Poison Limit Reached",
	"Permanent Media Failure",
	"Aborted",
	"Invalid Security State",
	"Incorrect Passphrase",
	"Unsupported Mailbox",
	"Invalid Payload Length",
}

Mailbox return codes

View Source 
var PCI_MMCONFIG_BASE_ADDR int64

Base address of PCI memory mapped configurations

View Source 
var PciVendor map[string]string

Functions

func BitFieldRead 

func BitFieldRead(r io.Reader, data any) error

PCIE uses little endian

func CDAT_SSLBIS added in v1.3.0 

func CDAT_SSLBIS(entryCnt uint) cdat_sslbis

func CDAT_read_Entry_Request added in v1.3.0 

func CDAT_read_Entry_Request(entryHandle uint32) uint32

// CDAT request and response struct

func CEDT_CXL_FIXED_MEMORY_WINDOW added in v1.2.0 

func CEDT_CXL_FIXED_MEMORY_WINDOW(Record_Length uint) cedt_cxl_fixed_memory_window_struct

func CEDT_CXL_XOR_INTERLEAVE_MATH added in v1.2.0 

func CEDT_CXL_XOR_INTERLEAVE_MATH(Record_Length uint) cedt_cxl_xor_interleave_math_struct

func CLEAR_EVENT_RECORDS_INPUT 

func CLEAR_EVENT_RECORDS_INPUT(Record_Count uint) clear_event_records_output

func CMPREG_HDM_DECODER_CAP added in v1.2.0 

func CMPREG_HDM_DECODER_CAP(Size uint) cmpreg_hdm_decoder_cap_struct

func DOE_DATA_OBJECT added in v1.3.0 

func DOE_DATA_OBJECT(DW_L uint) doe_data_object

func GET_EVENT_RECORDS_OUTPUT 

func GET_EVENT_RECORDS_OUTPUT(Record_Count uint) get_event_records_output

func GET_LOG_OUTPUT 

func GET_LOG_OUTPUT(Length uint) get_log_output

func GET_SUPPORTED_LOGS_OUTPUT 

func GET_SUPPORTED_LOGS_OUTPUT(Entries uint) get_supported_logs_output

func InitCxlDevList 

func InitCxlDevList() map[string]*CxlDev

obtain a list of CXL devices on the host

func REGISTER_LOCATOR 

func REGISTER_LOCATOR(Size uint) registerLocator

func ReadByBit 

func ReadByBit(r io.Reader, buf []byte, m []int)

func StructSize added in v1.2.0 

func StructSize(s any) int

StructSize returns the size of a structure in Bytes

func TRASFER_FW_INPUT 

func TRASFER_FW_INPUT(transfer_size uint) trasfer_fw_input

func UintToBool 

func UintToBool(i bitfield_1b) bool

convert integer to bool

Types

type ACPI 

type ACPI struct {
	CEDT []byte
}

func (*ACPI) CedtHeaderSize added in v1.2.0 

func (a *ACPI) CedtHeaderSize() int

Get cedt header struct size in bytes

func (*ACPI) FetchCedt 

func (a *ACPI) FetchCedt()

Update local copy of the cedt .

func (*ACPI) GetCedtHeader added in v1.2.0 

func (a *ACPI) GetCedtHeader() *ACPI_HEADER

Get cedt header struct

func (*ACPI) GetCedtSubtable 

func (a *ACPI) GetCedtSubtable(ofs int) interface{}

Get subtable cedt struct by offset.

func (*ACPI) GetCedtSubtableSize added in v1.2.0 

func (a *ACPI) GetCedtSubtableSize(ofs int) int

Get subtable cedt struct size in bytes.

type ACPI_HEADER 

type ACPI_HEADER struct {
	Signature             [4]byte
	Table_Length          uint32
	Revision              uint8
	Checksum              byte
	Oem_ID                [6]byte
	Oem_Table_ID          [8]byte
	Oem_Revision          uint32
	Asl_Compiler_ID       [4]byte
	Asl_Compiler_Revision uint32
}

define for Advanced Configuration and Power Interface (ACPI) header

type BACKGROUND_COMMAND_STATUS_REGISTER 

type BACKGROUND_COMMAND_STATUS_REGISTER struct {
	Command_Opcode                  bitfield_16b
	Percentage_Complete             bitfield_7b
	Reserved                        bitfield_9b
	Return_Code                     bitfield_16b
	Vendor_Specific_Extended_Status bitfield_16b
}

type BAR 

type BAR struct {
	Region_Type  bitfield_1b
	Locatable    bitfield_2b
	Prefetchable bitfield_1b
	Base_Address bitfield_28b
}

type BDF 

type BDF struct {
	Domain   uint16 `json:"Domain"`
	Bus      uint8  `json:"Bus"`
	Device   uint8  `json:"Device"`
	Function uint8  `json:"Function"`
}

type CDAT_DSEMTS added in v1.3.0 

type CDAT_DSEMTS struct {
	Type                          uint8
	Reserved                      uint8
	Length                        uint16
	Handle                        uint8
	EFI_Memory_Type_and_Attribute uint8
	Reserved2                     uint16
	DPA_Offset                    uint64
	DPA_Length                    uint64
}

4 Device Scoped EFI Memory Type Structure (DSEMTS)

type CDAT_DSIS added in v1.3.0 

type CDAT_DSIS struct {
	Type      uint8
	Reserved  uint8
	Length    uint16
	Flags     uint8
	Handle    uint8
	Reserved2 uint16
}

3 Device Scoped Initiator Structure (DSIS)

type CDAT_DSLBIS added in v1.3.0 

type CDAT_DSLBIS struct {
	Type            uint8
	Reserved        uint8
	Length          uint16
	Handle          uint8
	Flags           uint8
	Data_Type       uint8
	Reserved2       uint8
	Entry_Base_Unit uint64
	Entry           [3]uint16
	Reserved3       uint16
}

1 Device Scoped Latency and Bandwidth Information Structure (DSLBIS)

type CDAT_DSMAS added in v1.3.0 

type CDAT_DSMAS struct {
	Type        uint8
	Reserved    uint8
	Length      uint16
	DSMADHandle uint8
	Flags       uint8
	Reserved2   uint16
	DPA_Base    uint64
	DPA_Length  uint64
}

0 Device Scoped Memory Affinity Structure (DSMAS)

type CDAT_DSMSCIS added in v1.3.0 

type CDAT_DSMSCIS struct {
	Type                   uint8
	Reserved               uint8
	Length                 uint16
	Handle                 uint8
	Reserved2              [3]uint8
	Memory_Side_Cache_Size uint64
	Cache_Attributes       uint32
}

2 Device Scoped Memory Side Cache Information Structure (DSMSCIS)

type CDAT_SSLBE added in v1.3.0 

type CDAT_SSLBE struct {
	Port_X_ID            uint16
	Port_Y_ID            uint16
	Latency_or_Bandwidth uint16
	Reserved             uint16
}

5 Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) // Switch Scoped Latency and Bandwidth Entry (SSLBE)

type CDAT_header added in v1.3.0 

type CDAT_header struct {
	Table_Access_Response uint8
	Table_Type            uint8
	EntryHandle           uint16
	TableEntry            []uint8
}

func CDAT_read_Entry_Response added in v1.3.0 

func CDAT_read_Entry_Response(entryCnt uint) CDAT_header

type CEDT_CXL_HOST_BRIDGE added in v1.2.0 

type CEDT_CXL_HOST_BRIDGE struct {
	Type          byte
	Reserved      byte
	Record_Length uint16
	UID           uint32
	CXL_Version   uint32
	Reserved2     uint32
	Base          uint64
	Length        uint64
}

type CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRCUT added in v1.2.0 

type CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRCUT struct {
	Type                byte
	Reserved            byte
	Record_Length       uint16
	RCEC_Segment_Number uint16
	RCEC_BDF            uint16
	Protocol_Type       byte
	Base_Address        uint64
}
type CMPREG_LINK_CAP struct {
	CXL_Link_Layer_Capability_Register        uint32
	CXL_Link_Control_and_Status_Register      uint32
	CXL_Link_Rx_Credit_Control_Register       uint32
	CXL_Link_Rx_Credit_Return_Status_Register uint32
	CXL_Link_Tx_Credit_Status_Register        uint32
	CXL_Link_Ack_Timer_Control_Register       uint32
	CXL_Link_Defeature_Register               uint32
}

type CMPREG_RAS_CAP added in v1.2.0 

type CMPREG_RAS_CAP struct {
	Uncorrectable_Error_Status_Register   uint32
	Uncorrectable_Error_Mask_Register     uint32
	Uncorrectable_Error_Severity_Register uint32
	Correctable_Error_Status_Register     uint32
	Correctable_Error_Mask_Register       uint32
	Error_Capability_and_Control_Register uint32
	Header_Log_Registers                  uint32
}

type COMMAND_REGISTER 

type COMMAND_REGISTER struct {
	Command_Opcode bitfield_16b
	Payload_Length bitfield_21b
	Reserved       bitfield_27b
}

type COMPONENT_CAPABILITIES_HEADER added in v1.2.0 

type COMPONENT_CAPABILITIES_HEADER struct {
	Capability_ID      uint16
	Capability_Version bitfield_4b
	Capability_Pointer bitfield_12b
}

type COMPONENT_REG_HEADER added in v1.2.0 

type COMPONENT_REG_HEADER struct {
	Capability_ID      uint16
	Capability_Version bitfield_4b
	Cache_Mem_Version  bitfield_4b
	Array_Size         uint8
}

type CXL2_0_EXR_DVESC 

type CXL2_0_EXR_DVESC struct {
	PCIE_ext_cap_hdr            PCIE_EXT_CAP_HDR
	CXL_Port_Ext_Stat           CXL_PORT_EXT_STAT
	Port_Ctrl_Ext               PORT_CTRL_EXT
	Alt_Bus_Base                uint8
	Alt_Bus_Limit               uint8
	Alt_Mem_Base                uint16
	Alt_Mem_Limit               uint16
	Alt_Prefetch_Mem_Base       uint16
	Alt_Prefetch_Mem_Limit      uint16
	Alt_Prefetch_Mem_Base_High  uint32
	Alt_Prefetch_Mem_Limit_High uint32
	CXL_RCRB_Base               CXL_RCRB_BASE
	CXL_RCRB_Base_High          uint32
}

type CXLMailbox added in v1.2.0 

type CXLMailbox struct {
	// contains filtered or unexported fields
}

func (*CXLMailbox) Mailbox_cmd added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd(opcode uint16, payload []byte) (uint16, []byte)

General mailbox command flow

func (*CXLMailbox) Mailbox_cmd_clear_event_records added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_clear_event_records(event uint8) uint16

func (*CXLMailbox) Mailbox_cmd_get_event_interrupt_policy added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_get_event_interrupt_policy() *GET_EVENT_INTERRUPT_POLICY_OUTPUT

func (*CXLMailbox) Mailbox_cmd_get_event_records added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_get_event_records(event uint8) *get_event_records_output

//////////////////////////////////////// Mailbox command for each Opcode

func (*CXLMailbox) Mailbox_cmd_get_fw_info added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_get_fw_info() *GET_FW_INFO_OUTPUT

func (*CXLMailbox) Mailbox_cmd_get_log added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_get_log(log_input [16]byte, offset uint32, length uint32) *get_log_output

func (*CXLMailbox) Mailbox_cmd_get_supported_logs added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_get_supported_logs() *get_supported_logs_output

func (*CXLMailbox) Mailbox_cmd_identify_memory_device added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_identify_memory_device() *IDENTIFY_MEMORY_DEVICE_OUTPUT

func (*CXLMailbox) Mailbox_cmd_set_event_interrupt_policy added in v1.2.0 

func (mb *CXLMailbox) Mailbox_cmd_set_event_interrupt_policy(setting []int) uint16

func (*CXLMailbox) SendMailboxCCIbyOPCODE added in v1.3.0 

func (mb *CXLMailbox) SendMailboxCCIbyOPCODE(opcode uint64, args ...interface{}) interface{}

OPCODE translate

type CXL_CAP 

type CXL_CAP struct {
	Cache_Cap               bitfield_1b
	IO_Cap                  bitfield_1b
	Mem_Cap                 bitfield_1b
	Mem_HwInit_Mode         bitfield_1b
	HDM_Count               bitfield_2b
	Cache_Writeback         bitfield_1b
	CXL_reset_Cap           bitfield_1b
	CXL_reset_timeout       bitfield_3b
	CXL_reset_mem_clr_cap   bitfield_1b
	RsvdP                   bitfield_1b
	Multiple_Logical_Device bitfield_1b
	Viral_Cap               bitfield_1b
	PM_Init_comp            bitfield_1b
}

type CXL_CAP2 

type CXL_CAP2 struct {
	Cache_Size_Unit bitfield_4b
	RsvdP           bitfield_4b
	Cache_Size      bitfield_8b
}

type CXL_CTRL 

type CXL_CTRL struct {
	Cache_En             bitfield_1b
	IO_En                bitfield_1b
	Mem_En               bitfield_1b
	Cache_SF_Coverage    bitfield_5b
	Cache_SF_Granularity bitfield_3b
	Cache_Clean_Eviction bitfield_1b
	RsvdP                bitfield_2b
	Viral_En             bitfield_1b
	RsvdP2               bitfield_1b
}

type CXL_CTRL2 

type CXL_CTRL2 struct {
	Disable_Caching      bitfield_1b
	Init_Cache_WriteBack bitfield_1b
	Init_CXL_Rest        bitfield_1b
	CXL_Reset_Mem_Clr_En bitfield_1b
	RsvdP                bitfield_12b
}

type CXL_LOCK 

type CXL_LOCK struct {
	CONFIG_LOCK bitfield_1b
	RsvdP       bitfield_15b
}

type CXL_PORT_EXT_STAT 

type CXL_PORT_EXT_STAT struct {
	Port_Power_Mangement_Initialized bitfield_1b
	RsvdP                            bitfield_13b
	Viral_Stat                       bitfield_1b
	RsvdP2                           bitfield_1b
}

CXL2_0_EXR_DVESC

type CXL_RANGE_BASE_HIGH 

type CXL_RANGE_BASE_HIGH struct {
	Memory_Base_High uint32
}

type CXL_RANGE_BASE_LOW 

type CXL_RANGE_BASE_LOW struct {
	RsvdP           bitfield_28b
	Memory_Base_Low bitfield_4b
}

type CXL_RANGE_SIZE_HIGH 

type CXL_RANGE_SIZE_HIGH struct {
	Memory_Size_High uint32
}

type CXL_RANGE_SIZE_LOW 

type CXL_RANGE_SIZE_LOW struct {
	Memory_info_Valid     bitfield_1b
	Memory_Active         bitfield_1b
	Media_Type            bitfield_3b
	Memory_Class          bitfield_3b
	Desired_Interleave    bitfield_5b
	Memory_Active_Timeout bitfield_3b
	RsvdP                 bitfield_12b
	Memory_Size_low       bitfield_4b
}

type CXL_RCRB_BASE 

type CXL_RCRB_BASE struct {
	CXL_RCRB_En            bitfield_1b
	RsvdP                  bitfield_12b
	CXL_RCRB_Base_Addr_Low bitfield_19b
}

type CXL_STAT 

type CXL_STAT struct {
	RsvdP      bitfield_14b
	Viral_Stat bitfield_1b
	RsvdP2     bitfield_1b
}

type CXL_STAT2 

type CXL_STAT2 struct {
	Cache_Invalid     bitfield_1b
	CXL_Rest_Complete bitfield_1b
	CXL_Reset_Error   bitfield_1b
	RsvdP             bitfield_12b
	PM_Init_Complete  bitfield_1b
}

type Coherent_Device_Attribute_Table_Header added in v1.3.0 

type Coherent_Device_Attribute_Table_Header struct {
	Length   uint32
	Revision uint8
	Checksum uint8
	Reserved [6]uint8
	Sequence uint32
}

type ComponentRegistersPtr added in v1.2.0 

type ComponentRegistersPtr struct {
	Ras_Cap         *CMPREG_RAS_CAP
	Link_Cap        *CMPREG_LINK_CAP
	HDM_Decoder_Cap *cmpreg_hdm_decoder_cap_struct
}

type CxlCaps 

type CxlCaps struct {
	Cache_Cap bool
	IO_Cap    bool
	Mem_Cap   bool
	Cache_En  bool
	IO_En     bool
	Mem_En    bool
}

Capability struct for CXL device

type CxlDev 

type CxlDev struct {
	Bdf        *BDF                   `json:"BDF"`
	PCIE       []byte                 `json:"-"`
	Memdev     *MemoryDeviceRegisters `json:"-"`
	CmpReg     *ComponentRegistersPtr `json:"-"`
	MailboxCCI *CXLMailbox            `json:"-"`
	Cdat       *DOE_CAP               `json:"-"`
}

func (*CxlDev) CDAT_init added in v1.3.0 

func (c *CxlDev) CDAT_init()

Initialize CDAT struct if available

func (*CxlDev) GetBdfString 

func (c *CxlDev) GetBdfString() string

return the BDF as string BUS:DEV.FUN

func (*CxlDev) GetCxlCap 

func (c *CxlDev) GetCxlCap() CxlCaps

return the capacities info of the CXL device

func (*CxlDev) GetCxlRev 

func (c *CxlDev) GetCxlRev() CxlRev

return the CXL revision

func (*CxlDev) GetCxlType 

func (c *CxlDev) GetCxlType() CxlDevType

return the type info of the CXL device ( type 1/ type 2/ type 3 ) Type 1 - CXL.cache and CXL.io Type 2 - CXM.mem and CXL.cache and CXL.io Type 3 - CXL.mem and CXL.io

func (*CxlDev) GetDeviceInfo 

func (c *CxlDev) GetDeviceInfo() string

return the Vendor Info of the PCIe/CXL device

func (*CxlDev) GetDvsec 

func (c *CxlDev) GetDvsec(dvsecId cxl_dvsec_id) interface{}

return the struct of a DVSEC

func (*CxlDev) GetDvsecList 

func (c *CxlDev) GetDvsecList() map[cxl_dvsec_id]uint32

return a list of DVSEC tables from the CXL device

func (*CxlDev) GetMemDevRegStruct added in v1.2.0 

func (c *CxlDev) GetMemDevRegStruct(i int) any

parse mem dev register from index

func (*CxlDev) GetMemoryBaseAddr 

func (c *CxlDev) GetMemoryBaseAddr() int64

return the memory base of a CXL device

func (*CxlDev) GetMemorySize 

func (c *CxlDev) GetMemorySize() int64

return the memory size of a CXL device Memory_Size_High: Corresponds to bits 63:32 of the CXL Range 1 memory size regardless of whether the device implements CXL HDM Decoder Capability registers. Memory_Size_Low: Corresponds to bits 31:28 of the CXL Range 1 memory size regardless of whether the device implements CXL HDM Decoder Capability registers.

func (*CxlDev) GetPcieHdr 

func (c *CxlDev) GetPcieHdr() *PCIE_CONFIG_HDR

return the pcie header struct

func (*CxlDev) GetSerialNumber added in v1.2.0 

func (c *CxlDev) GetSerialNumber() string

func (*CxlDev) GetVendorInfo 

func (c *CxlDev) GetVendorInfo() string

return the Vendor Info of the PCIe/CXL device

func (*CxlDev) MeasureBandwidth added in v1.3.0 

func (c *CxlDev) MeasureBandwidth() (float64, error)

measure bandwidth -- the whole memory has to be offlined

func (*CxlDev) MeasureLatency added in v1.3.0 

func (c *CxlDev) MeasureLatency() (uint64, error)

measure latency -- the memory has to be offlined

type CxlDevType 

type CxlDevType string

CxlDevType : The type of the CXL device, ie type 1, 2, 3. 

const (
	CXL_UNKOWN_DEV CxlDevType = "CXLDeviceTypeUnkown"
	CXL_TYPE1_DEV  CxlDevType = "CXLType1Device"
	CXL_TYPE2_DEV  CxlDevType = "CXLType2Device"
	CXL_TYPE3_DEV  CxlDevType = "CXLType3Device"
)

List of CXL device types

type CxlMemAttr 

type CxlMemAttr struct {
	AccessLatencyPs    uint64
	ReadLatencyPs      uint64
	WriteLatencyPs     uint64
	AccessBandwidthMBs uint64
	ReadBandwidthMBs   uint64
	WriteBandwidthMBs  uint64
}

Memory Attribute table for CXL memory perforrmance

type CxlRev 

type CxlRev string

CxlRev : The revision the CXL device, ie rev 1.1, 2.0, 3.0. 

const (
	CXL_REV_UNKOWN CxlRev = "CXL_unkown"
	CXL_REV_1_1    CxlRev = "CXL1.1"
	CXL_REV_2_0    CxlRev = "CXL2.0"
	CXL_REV_3_0    CxlRev = "CXL3.0"
	CXL_INVALID    CxlRev = "NotCXL"
)

List of CXL revisions

type DEVICE_CAPABILITIES_ARRAY_REGISTER added in v1.2.0 

type DEVICE_CAPABILITIES_ARRAY_REGISTER struct {
	Capability_ID      uint16
	Version            uint8
	Reserved           uint8
	Capabilities_Count uint16
	Reserved2          [10]uint8
}

define for CXL Memory Device Registers struct

type DEVICE_CAPABILITIES_HEADER added in v1.2.0 

type DEVICE_CAPABILITIES_HEADER struct {
	Capability_ID uint16
	Version       uint8
	Reserved      uint8
	Offset        uint32
	Length        uint32
	Reserved2     uint32
}

type DOE_CAP added in v1.3.0 

type DOE_CAP struct {
	CDAT_valid bool
	// contains filtered or unexported fields
}

func (*DOE_CAP) Get_CDAT_DSLBIS_performance added in v1.3.0 

func (cdat *DOE_CAP) Get_CDAT_DSLBIS_performance() CxlMemAttr

func (*DOE_CAP) PrintAllCDAT added in v1.3.0 

func (cdat *DOE_CAP) PrintAllCDAT()

type DOE_Discovery_Response added in v1.3.0 

type DOE_Discovery_Response struct {
	Vendor_Id            uint16
	Data_Object_Protocol uint8
	Next_Index           uint8
}

// response struct

type DVSEC_FLEX_BUS_PORT_CAP 

type DVSEC_FLEX_BUS_PORT_CAP struct {
	Cache_Cap           bitfield_1b
	IO_Cap              bitfield_1b
	Mem_Cap             bitfield_1b
	RsvdP               bitfield_2b
	CXL2p0_Cap          bitfield_1b
	CXL_Multi_logic_cap bitfield_1b
	RsvdP2              bitfield_9b
}

PCIE_DVSEC_FOR_FLEX_BUS_PORT

type DVSEC_FLEX_BUS_PORT_CTRL 

type DVSEC_FLEX_BUS_PORT_CTRL struct {
	Cache_En                bitfield_1b
	IO_En                   bitfield_1b
	Mem_En                  bitfield_1b
	CXL_Sync_Hdr_Bypass_en  bitfield_1b
	Drift_buffer_En         bitfield_1b
	CXL2p0_En               bitfield_1b
	CXL_Multi_logic_En      bitfield_1b
	Disable_CXL1p1_Training bitfield_1b
	Retimer1_Present        bitfield_1b
	Retimer2_Present        bitfield_1b
	RsvdP2                  bitfield_6b
}

type DVSEC_FLEX_BUS_PORT_STAT 

type DVSEC_FLEX_BUS_PORT_STAT struct {
	Cache_En                          bitfield_1b
	IO_En                             bitfield_1b
	Mem_En                            bitfield_1b
	CXL_Sync_Hdr_Bypass_en            bitfield_1b
	Drift_buffer_En                   bitfield_1b
	CXL2p0_En                         bitfield_1b
	CXL_Multi_logic_En                bitfield_1b
	RsvdP                             bitfield_1b
	CXL_Cor_Protocol_ID_Fram_Err      bitfield_1b
	CXL_unCor_Protocol_ID_Fram_Err    bitfield_1b
	CXL_UnExpct_Protocol_ID_Dropped   bitfield_1b
	Retimer_Present_Mismatched        bitfield_1b
	FlexBusEnableBits_Phase2_Mismatch bitfield_1b
	RsvdP2                            bitfield_3b
}

type DVSEC_FLEX_BUS_PORT_TS 

type DVSEC_FLEX_BUS_PORT_TS struct {
	Received_Flex_Bus_Data_Phase1 bitfield_24b
	RsvdP                         bitfield_8b
}

type DVSEC_HDR1 

type DVSEC_HDR1 struct {
	DVSEC_Vendor_ID bitfield_16b
	DVSEC_Rev       bitfield_4b
	DVSEC_Length    bitfield_12b
}

Designated Vendor-Specific Extended Capability (DVSEC)

type DVSEC_HDR2 

type DVSEC_HDR2 struct {
	DVSEC_ID uint16
}

type GET_EVENT_INTERRUPT_POLICY_OUTPUT 

type GET_EVENT_INTERRUPT_POLICY_OUTPUT struct {
	Informational_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS
	Warning_Event_Log_Interrupt_Settings       INTERRUPT_SETTINGS
	Failure_Event_Log_Interrupt_Settings       INTERRUPT_SETTINGS
	Fatal_Event_Log_Interrupt_Settings         INTERRUPT_SETTINGS
}

type GET_FW_INFO_OUTPUT 

type GET_FW_INFO_OUTPUT struct {
	FW_Slots_Supported         uint8
	FW_Slot_Info               uint8
	FW_Activation_Capabilities uint8
	Reserved                   [13]uint8
	Slot_FW                    [4]SLOT_FW_REVISION
}

type GET_LOG_INPUT 

type GET_LOG_INPUT struct {
	Log_Identifier [16]byte //0x10
	Offset         uint32
	Length         uint32
}

type GPF_DVSEC_FOR_DEV 

type GPF_DVSEC_FOR_DEV struct {
	PCIE_ext_cap_hdr       PCIE_EXT_CAP_HDR
	GPF_Phase2_Duration    GPF_PHASE2_DURATION
	GPF_Phase2_Power_in_mW uint32
}

type GPF_DVSEC_FOR_PORTS 

type GPF_DVSEC_FOR_PORTS struct {
	PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR
	RsvdP            uint16
	GPF_Phase1_Ctrl  GPF_PHASE_CTRL
	GPF_Phase2_Ctrl  GPF_PHASE_CTRL
}

type GPF_PHASE2_DURATION 

type GPF_PHASE2_DURATION struct {
	Device_GPF_Phase_2_Time_base  bitfield_4b
	RsvdP                         bitfield_4b
	Device_GPF_Phase_2_Time_Scale bitfield_4b
	RsvdP2                        bitfield_4b
}

GPF_DVSEC_FOR_DEV

type GPF_PHASE_CTRL 

type GPF_PHASE_CTRL struct {
	Port_GPF_Phase_TO_base  bitfield_4b
	RsvdP                   bitfield_4b
	Port_GPF_Phase_TO_Scale bitfield_4b
	RsvdP2                  bitfield_4b
}

GPF_DVSEC_FOR_PORTS

type HDM_DECODER added in v1.2.0 

type HDM_DECODER struct {
	Base_Low      uint32
	Base_High     uint32
	Size_Low      uint32
	Size_High     uint32
	Control       uint32
	DPA_Skip_Low  uint32
	DPA_Skip_High uint32
	Reserved      uint32
}

type HDM_DECODER_CAP added in v1.2.0 

type HDM_DECODER_CAP struct {
	Decoder_Cnt                       bitfield_4b
	Target_Cnt                        bitfield_4b
	A11to8_Interleave_Capable         bitfield_1b
	A14to12_Interleave_Capable        bitfield_1b
	Poison_On_Decode_Error_Capability bitfield_1b
	Interleave_Capable_3_6_12_Way_    bitfield_1b
	Interleave_Capable_16_Way         bitfield_1b
	UIO_Capable                       bitfield_1b
	Reserved                          bitfield_2b
	UIO_Capable_Decoder_Count         bitfield_4b
	MemData_NXM_Capable               bitfield_1b
	Reserved2                         bitfield_11b
}

type HDM_DECODER_GLOBAL_CONTROL added in v1.2.0 

type HDM_DECODER_GLOBAL_CONTROL struct {
	Poison_On_Decod_Err_En bitfield_1b
	HDMM_Decoder_En        bitfield_1b
	Reserved               bitfield_30b
}

type IDENTIFY_MEMORY_DEVICE_OUTPUT 

type IDENTIFY_MEMORY_DEVICE_OUTPUT struct {
	FW_Revision                             [16]byte //0x10
	Total_Capaciity                         uint64
	Volatile_Only_Capacity                  uint64
	Persistent_Only_Capacitgy               uint64
	Partition_Aliggnment                    uint64
	Informational_Event_Log_Size            uint16
	Warning_Event_Log_Size                  uint16
	Failure_Event_Log_Size                  uint16
	Fatal_Event_Log_Size                    uint16
	LSA_Size                                uint32
	Poison_List_Maximum_Media_Error_Records [3]uint8
	Inject_Poison_Limit                     uint16
	Poison_Handling_Capabilities            uint8
	Qos_Telemetry_Capabilities              uint8
}

type INTERRUPT_SETTINGS 

type INTERRUPT_SETTINGS struct {
	Interrupt_Mode           bitfield_2b
	Reserved                 bitfield_2b
	Interrupt_Message_Number bitfield_4b
}

type MAILBOX_CAPABILITIES_REGISTER 

type MAILBOX_CAPABILITIES_REGISTER struct {
	Payload_Size                                  bitfield_5b
	MB_Doorbell_Interrupt_Capable                 bitfield_1b
	Background_Command_Complete_Interrupt_Capable bitfield_1b
	Interrupt_Message_Number                      bitfield_4b
	Reserved                                      bitfield_21b
}

type MAILBOX_CONTROL_REGISTER 

type MAILBOX_CONTROL_REGISTER struct {
	Doorbell                              bitfield_1b
	MB_Doorbell_Interrupt                 bitfield_1b
	Background_Command_Complete_Interrupt bitfield_1b
	Reserved                              bitfield_29b
}

type MAILBOX_STATUS_REGISTER 

type MAILBOX_STATUS_REGISTER struct {
	Background_Operation            bitfield_1b
	Reserved                        bitfield_31b
	Return_Code                     bitfield_16b
	Vendor_Specific_Extended_Status bitfield_16b
}

type MEMDEV_DEVICE_STATUS added in v1.2.0 

type MEMDEV_DEVICE_STATUS struct {
	Event_Status uint32
	Reserved     uint32
}

type MEMDEV_MEMDEV_STATUS added in v1.2.0 

type MEMDEV_MEMDEV_STATUS struct {
	Device_Fatal             bitfield_1b
	FW_Halt                  bitfield_1b
	Media_Status             bitfield_2b
	Mailbox_Interfaces_Ready bitfield_1b
	Reset_Needed             bitfield_3b
	Reserved                 bitfield_24b
	Reserved2                uint32
}

type MLD 

type MLD struct {
	PCIE_ext_cap_hdr       PCIE_EXT_CAP_HDR
	Num_LDs_Supported      uint16
	LD_ID_Hot_Reset_Vector uint16
	RsvdP                  uint16
}

MLD

type MemoryDeviceRegisters added in v1.2.0 

type MemoryDeviceRegisters struct {
	Device_Capabilities_Array_Register DEVICE_CAPABILITIES_ARRAY_REGISTER
	Device_Capability_Header           []DEVICE_CAPABILITIES_HEADER
	Device_Capability                  []byte
}

func CXL_MEMORY_DEVICE_REGISTERS 

func CXL_MEMORY_DEVICE_REGISTERS(count uint, size uint) MemoryDeviceRegisters

func (*MemoryDeviceRegisters) GetCapabilityByteArray added in v1.2.0 

func (m *MemoryDeviceRegisters) GetCapabilityByteArray(i int) []byte

type NON_CXL_FUNC_MAP 

type NON_CXL_FUNC_MAP struct {
	PCIE_ext_cap_hdr    PCIE_EXT_CAP_HDR
	RsvdP               uint16
	Non_CXL_Fun_Map_Reg [8]uint32
}

NON_CXL_FUNC_MAP

type PCIE_CLASS_CODE 

type PCIE_CLASS_CODE struct {
	Prog_if         uint8
	Sub_Class_Code  uint8
	Base_Class_Code uint8
}

define for PCIE config space struct

type PCIE_CONFIG_HDR 

type PCIE_CONFIG_HDR struct {
	Vendor_ID              uint16
	Device_ID              uint16
	Command                uint16
	Status                 int16
	Rev_ID                 uint8
	Class_Code             PCIE_CLASS_CODE
	Misc                   uint32
	Base_Address_Registers [6]BAR
	Misc2                  [6]int32
}

type PCIE_DEVICE_SERIAL_NUMBER_CAP added in v1.2.0 

type PCIE_DEVICE_SERIAL_NUMBER_CAP struct {
	PCIE_ext_cap_ID bitfield_16b
	Cap_Ver         bitfield_4b
	Next_Cap_ofs    bitfield_12b
	SN_low          uint32
	SN_high         uint32
}

type PCIE_DOE_EXT_CAP added in v1.3.0 

type PCIE_DOE_EXT_CAP struct {
	PCIE_ext_cap_hdr       uint32
	DOE_Capabilities       uint32
	DOE_Control            uint32
	DOE_Status             uint32
	DOE_Write_Data_Mailbox uint32
	DOE_Read_Data_Mailbox  uint32
}

type PCIE_DOE_HEADER1 added in v1.3.0 

type PCIE_DOE_HEADER1 struct {
	Vendor_ID uint16
	DO_type   uint8
	Reserved  uint8
}

type PCIE_DOE_HEADER2 added in v1.3.0 

type PCIE_DOE_HEADER2 struct {
	Length   bitfield_18b
	Reserved bitfield_14b
}

type PCIE_DVSEC_FOR_CXL 

type PCIE_DVSEC_FOR_CXL struct {
	PCIE_ext_cap_hdr     PCIE_EXT_CAP_HDR
	CXL_cap              CXL_CAP
	CXL_ctrl             CXL_CTRL
	CXL_stat             CXL_STAT
	CXL_ctrl2            CXL_CTRL2
	CXL_stat2            CXL_STAT2
	CXL_lock             CXL_LOCK
	CXL_cap2             CXL_CAP2
	CXL_range1_size_high CXL_RANGE_SIZE_HIGH
	CXL_range1_size_low  CXL_RANGE_SIZE_LOW
	CXL_range1_base_high CXL_RANGE_BASE_HIGH
	CXL_range1_base_low  CXL_RANGE_BASE_LOW
	CXL_range2_size_high CXL_RANGE_SIZE_HIGH
	CXL_range2_size_low  CXL_RANGE_SIZE_LOW
	CXL_range2_base_high CXL_RANGE_BASE_HIGH
	CXL_range2_base_low  CXL_RANGE_BASE_LOW
}

type PCIE_DVSEC_FOR_FLEX_BUS_PORT 

type PCIE_DVSEC_FOR_FLEX_BUS_PORT struct {
	PCIE_ext_cap_hdr                           PCIE_EXT_CAP_HDR
	DVSEC_flex_bus_port_cap                    DVSEC_FLEX_BUS_PORT_CAP
	DVSEC_flex_bus_port_control                DVSEC_FLEX_BUS_PORT_CTRL
	DVSEC_flex_bus_port_Status                 DVSEC_FLEX_BUS_PORT_STAT
	DVSEC_flex_bus_received_mod_TS_data_phase1 DVSEC_FLEX_BUS_PORT_TS
}

type PCIE_DVSEC_FOR_TEST_CAP 

type PCIE_DVSEC_FOR_TEST_CAP struct {
	PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR
}

type PCIE_EXT_CAP_HDR 

type PCIE_EXT_CAP_HDR struct {
	PCIE_ext_cap_ID bitfield_16b
	Cap_Ver         bitfield_4b
	Next_Cap_ofs    bitfield_12b
	DVSEC_hdr1      DVSEC_HDR1
	DVSEC_hdr2      DVSEC_HDR2
}

type PORT_CTRL_EXT 

type PORT_CTRL_EXT struct {
	Unmask_SBR              bitfield_1b
	Unmask_Link_Disable     bitfield_1b
	Alt_Mem_and_ID_Space_En bitfield_1b
	Alt_BME                 bitfield_1b
	RsvdP                   bitfield_10b
	Viral_En                bitfield_1b
	RsvdP2                  bitfield_1b
}

type REGISTER_BLOCK 

type REGISTER_BLOCK struct {
	Register_Offset_Low  REGISTER_OFFSET_LOW
	Register_Offset_High REGISTER_OFFSET_HIGH
}

type REGISTER_OFFSET_HIGH 

type REGISTER_OFFSET_HIGH struct {
	Register_Block_Offset_High uint32
}

type REGISTER_OFFSET_LOW 

type REGISTER_OFFSET_LOW struct {
	Register_BIR              bitfield_3b
	RsvdP                     bitfield_5b
	Register_Block_Identifier bitfield_8b
	Register_Block_Offset_Low bitfield_16b
}

REGISTER_LOCATOR

type SET_EVENT_INTERRUPT_POLICY_INPUT 

type SET_EVENT_INTERRUPT_POLICY_INPUT struct {
	Informational_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS
	Warning_Event_Log_Interrupt_Settings       INTERRUPT_SETTINGS
	Failure_Event_Log_Interrupt_Settings       INTERRUPT_SETTINGS
	Fatal_Event_Log_Interrupt_Settings         INTERRUPT_SETTINGS
}

type SLOT_FW_REVISION 

type SLOT_FW_REVISION struct {
	FW_Revision [16]byte
}

type SUPPORTED_LOG_ENTRY 

type SUPPORTED_LOG_ENTRY struct {
	Log_Identifier [16]byte //0x10
	Log_Size       uint32
}

Source Files

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