wag: github.com/tsavola/wag/internal/isa/arm/in Index | Files

package in

import "github.com/tsavola/wag/internal/isa/arm/in"

Index

Package Files

alias.go assume.go encode.go insn.go

Constants

const (
    EQ  = Cond(0x0) // equal to
    NE  = Cond(0x1) // not equal to
    CS  = Cond(0x2) // carry set
    CC  = Cond(0x3) // carry clear
    MI  = Cond(0x4) // minus, negative
    PL  = Cond(0x5) // positive or zero
    VS  = Cond(0x6) // signed overflow
    VC  = Cond(0x7) // no signed overflow
    HI  = Cond(0x8) // greater than (unsigned)
    LS  = Cond(0x9) // less than or equal to (unsigned)
    GE  = Cond(0xa) // greater than or equal to (signed)
    LT  = Cond(0xb) // less than (signed)
    GT  = Cond(0xc) // greater than (signed)
    LE  = Cond(0xd) // less than or equal to (signed)

    HS  = CS // greater than or equal to (unsigned)
    LO  = CC // less than (unsigned)
)
const (
    Unscaled = S(0 << 12)
    Scaled   = S(1 << 12)
)
const (
    LSL = Shift(0 << 22)
    LSR = Shift(1 << 22)
    ASR = Shift(2 << 22)
)
const (
    UXTB = Ext(0 << 13)
    UXTH = Ext(1 << 13)
    UXTW = Ext(2 << 13)
    UXTX = Ext(3 << 13)
    SXTB = Ext(4 << 13)
    SXTH = Ext(5 << 13)
    SXTW = Ext(6 << 13)
    SXTX = Ext(7 << 13)
)
const (
    // Compare & branch (immediate)
    CBZ  = RegImm19Size(0x1a<<25 | 0<<24)
    CBNZ = RegImm19Size(0x1a<<25 | 1<<24)

    // Conditional branch (immediate)
    Bc  = CondImm19(0x2a<<25 | 0<<24 | 0<<4)

    // Exception generation
    BRK = Imm16(0xd4<<24 | 1<<21 | 0<<2 | 0<<0)

    // Test & branch (immediate)
    TBZ  = RegImm14Bit(0x1b<<25 | 0<<24)
    TBNZ = RegImm14Bit(0x1b<<25 | 1<<24)

    // Unconditional branch (immediate)
    B   = Imm26(0<<31 | 5<<26)
    BL  = Imm26(1<<31 | 5<<26)

    // Unconditional branch (register)
    BR  = Reg(0x6b<<25 | 0<<21 | 0x1f<<16 | 0<<10 | 0<<0)
    BLR = Reg(0x6b<<25 | 1<<21 | 0x1f<<16 | 0<<10 | 0<<0)
    RET = Reg(0x6b<<25 | 2<<21 | 0x1f<<16 | 0<<10 | 0<<0)

    // Load/store register (immediate post-indexed)
    LDRpost = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 1<<22 | 0<<21 | 1<<10)

    // Load/store register (immediate pre-indexed)
    STRpre = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 0<<22 | 0<<21 | 3<<10)

    // Load/store register (register offset)
    LDRr = RegRegSOptionRegSize(1<<31 | 7<<27 | 0<<24 | 1<<22 | 1<<21 | 2<<10)

    // Load/store register (unscaled immediate)
    STUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 0<<22 | 0<<21 | 0<<10)
    LDUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<24 | 1<<22 | 0<<21 | 0<<10)

    // Load/store register (unsigned immediate)
    STR = RegRegImm12Size(1<<31 | 7<<27 | 1<<24 | 0<<22)
    LDR = RegRegImm12Size(1<<31 | 7<<27 | 1<<24 | 1<<22)

    // Add/subtract (immediate)
    ADDi  = RegRegImm12ShiftSf(0<<30 | 0<<29 | 0x11<<24)
    ADDSi = RegRegImm12ShiftSf(0<<30 | 1<<29 | 0x11<<24)
    SUBi  = RegRegImm12ShiftSf(1<<30 | 0<<29 | 0x11<<24)
    SUBSi = RegRegImm12ShiftSf(1<<30 | 1<<29 | 0x11<<24)

    // Bitfield
    UBFM = RegRegImm6Imm6NSf(2<<29 | 0x26<<23 | 0<<22)

    // Move wide (immediate)
    MOVN = RegImm16HwSf(0<<29 | 0x25<<23)
    MOVZ = RegImm16HwSf(2<<29 | 0x25<<23)
    MOVK = RegImm16HwSf(3<<29 | 0x25<<23)

    // Address generation
    ADR = RegImm19Imm2(0<<31 | 0x10<<24)

    // Add/subtract (extended register)
    ADDe  = RegRegImm3ExtRegSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<22 | 1<<21)
    SUBSe = RegRegImm3ExtRegSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<22 | 1<<21)

    // Add/subtract (shifted register)
    ADDs  = RegRegImm6RegShiftSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<21)
    SUBs  = RegRegImm6RegShiftSf(1<<30 | 0<<29 | 0x0b<<24 | 0<<21)
    SUBSs = RegRegImm6RegShiftSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<21)

    // Conditional select
    CSEL  = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 0<<10)
    CSINC = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 1<<10)

    // Logical (shifted register)
    ANDs  = RegRegImm6RegShiftSf(0<<29 | 0x0a<<24 | 0<<21)
    ORRs  = RegRegImm6RegShiftSf(1<<29 | 0x0a<<24 | 0<<21)
    ANDSs = RegRegImm6RegShiftSf(3<<29 | 0x0a<<24 | 0<<21)

    // Variable shift
    RORV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x0b<<10)

    // Bit operations
    RBIT = RegRegSf(1<<30 | 0<<29 | 0xd6<<21 | 0<<16 | 0<<10)
    CLZ  = RegRegSf(1<<30 | 0<<29 | 0xd6<<21 | 0<<16 | 4<<10)

    // Multiply
    MADD = RegRegRegRegSf(0<<29 | 0x1b<<24 | 0<<21 | 0<<15)
    MSUB = RegRegRegRegSf(0<<29 | 0x1b<<24 | 0<<21 | 1<<15)

    // Divide
    UDIV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x02<<10)
    SDIV = RegRegRegSf(0<<30 | 0<<29 | 0xd6<<21 | 0x03<<10)

    // Floating-point move (register)
    FMOV = RegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<17 | 0<<15 | 0x10<<10)

    // Floating-point move (general) - size arguments must be identical
    FMOVtog   = RegRegTypeSf(0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<19 | 6<<16 | 0<<10)
    FMOVfromg = RegRegTypeSf(0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<19 | 7<<16 | 0<<10)

    // Floating-point arithmetic (1 source)
    FNEG = RegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<17 | 2<<15 | 0x10<<10)

    // Floating-point comparison
    FCMP = DiscardRegRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 0<<14 | 8<<10 | 0<<3 | 0<<0)

    // Floating-point conditional select
    FCSEL = RegRegCondRegType(0<<31 | 0<<30 | 0<<29 | 0x1e<<24 | 1<<21 | 3<<10)

    // System register
    MSR_FPSR = SystemReg(0x354<<22 | 0<<21 | 1<<20 | 0xda21<<5)
    MRS_FPSR = SystemReg(0x354<<22 | 1<<21 | 1<<20 | 0xda21<<5)
)
const (
    AddsubAdd = Addsub(0)
    AddsubSub = Addsub(1)
)
const (
    LogicAnd = Logic(0)
    LogicOrr = Logic(1)
    LogicEor = Logic(2)
)
const (
    ExtendS = Bitfield(0)
    ExtendU = Bitfield(2)
)
const (
    DivisionUnsigned = DataProcessing2(0x2)
    DivisionSigned   = DataProcessing2(0x3)

    VariableShiftL  = DataProcessing2(0x8)
    VariableShiftLR = DataProcessing2(0x9)
    VariableShiftAR = DataProcessing2(0xa)
    VariableShiftRR = DataProcessing2(0xb)
)
const (
    //                            17     15
    UnaryFloatAbs     = UnaryFloat(0<<2 | 1<<0)
    UnaryFloatNeg     = UnaryFloat(0<<2 | 2<<0)
    UnaryFloatSqrt    = UnaryFloat(0<<2 | 3<<0)
    UnaryFloatCvtTo32 = UnaryFloat(1<<2 | 0<<0)
    UnaryFloatCvtTo64 = UnaryFloat(1<<2 | 1<<0)

    //                             18     15
    UnaryFloatRIntN = UnaryFloat(1<<3 | 0<<0)
    UnaryFloatRIntP = UnaryFloat(1<<3 | 1<<0)
    UnaryFloatRIntM = UnaryFloat(1<<3 | 2<<0)
    UnaryFloatRIntZ = UnaryFloat(1<<3 | 3<<0)
)
const (
    //                             13     12     10
    BinaryFloatAdd = BinaryFloat(1<<3 | 0<<2 | 2<<0)
    BinaryFloatSub = BinaryFloat(1<<3 | 1<<2 | 2<<0)

    //                             15     12     10
    BinaryFloatMul = BinaryFloat(0<<5 | 0<<2 | 2<<0)
    BinaryFloatDiv = BinaryFloat(1<<2 | 2<<0)

    //                             14     12     10
    BinaryFloatMax = BinaryFloat(1<<4 | 0<<2 | 2<<0)
    BinaryFloatMin = BinaryFloat(1<<4 | 1<<2 | 2<<0)
)
const (
    //                                   19     16
    ConvertIntS      = ConvertCategory(0<<3 | 2<<0) // SCVTF
    ConvertIntU      = ConvertCategory(0<<3 | 3<<0) // UCVTF
    ReinterpretFloat = ConvertCategory(0<<3 | 6<<0) // FMOV
    ReinterpretInt   = ConvertCategory(0<<3 | 7<<0) // FMOV
    TruncFloatS      = ConvertCategory(3<<3 | 0<<0) // FCVTZS
    TruncFloatU      = ConvertCategory(3<<3 | 1<<0) // FCVTZU
)
const (
    //                   30      27      26     22
    StoreB   = Memory(0<<14 | 7<<11 | 0<<10 | 0<<6)
    LoadB    = Memory(0<<14 | 7<<11 | 0<<10 | 1<<6)
    LoadSB64 = Memory(0<<14 | 7<<11 | 0<<10 | 2<<6)
    LoadSB32 = Memory(0<<14 | 7<<11 | 0<<10 | 3<<6)
    StoreH   = Memory(1<<14 | 7<<11 | 0<<10 | 0<<6)
    LoadH    = Memory(1<<14 | 7<<11 | 0<<10 | 1<<6)
    LoadSH64 = Memory(1<<14 | 7<<11 | 0<<10 | 2<<6)
    LoadSH32 = Memory(1<<14 | 7<<11 | 0<<10 | 3<<6)
    StoreW   = Memory(2<<14 | 7<<11 | 0<<10 | 0<<6)
    LoadW    = Memory(2<<14 | 7<<11 | 0<<10 | 1<<6)
    LoadSW64 = Memory(2<<14 | 7<<11 | 0<<10 | 2<<6)
    StoreF32 = Memory(2<<14 | 7<<11 | 1<<10 | 0<<6)
    LoadF32  = Memory(2<<14 | 7<<11 | 1<<10 | 1<<6)
    StoreD   = Memory(3<<14 | 7<<11 | 0<<10 | 0<<6)
    LoadD    = Memory(3<<14 | 7<<11 | 0<<10 | 1<<6)
    StoreF64 = Memory(3<<14 | 7<<11 | 1<<10 | 0<<6)
    LoadF64  = Memory(3<<14 | 7<<11 | 1<<10 | 1<<6)
)
const (
    RegFakeSP = reg.R(29)
)

func Int14 Uses

func Int14(i int32) uint32

func Int19 Uses

func Int19(i int32) uint32

func Int26 Uses

func Int26(i int32) uint32

func Int9 Uses

func Int9(i int32) uint32

func LogicalShiftLeft Uses

func LogicalShiftLeft(rd, rn reg.R, uimm uint32, t wa.Size) uint32

func PopReg Uses

func PopReg(r reg.R, t wa.Type) uint32

func PushReg Uses

func PushReg(r reg.R, t wa.Type) uint32

func Uint12 Uses

func Uint12(i uint64) uint32

func Uint16 Uses

func Uint16(i uint64) uint32

type Addsub Uses

type Addsub uint8

Add/subtract instruction's "op" field

func (Addsub) OpcodeImm Uses

func (op Addsub) OpcodeImm() RegRegImm12ShiftSf

func (Addsub) OpcodeRegExt Uses

func (op Addsub) OpcodeRegExt() RegRegImm3ExtRegSf

type BinaryFloat Uses

type BinaryFloat uint8

Floating-point (2 source) instruction's bits 10-15

func (BinaryFloat) OpcodeReg Uses

func (op BinaryFloat) OpcodeReg() RegRegRegType

type Bitfield Uses

type Bitfield uint8

Bitfield instruction’s "opc" field

func (Bitfield) Opcode Uses

func (op Bitfield) Opcode() RegRegImm6Imm6NSf

type Cond Uses

type Cond uint32

type CondImm19 Uses

type CondImm19 uint32

func (CondImm19) CondI19 Uses

func (op CondImm19) CondI19(cond Cond, imm uint32) uint32

type ConvertCategory Uses

type ConvertCategory uint8

Floating-point/integer instruction's "rmode" and "opcode" fields

func (ConvertCategory) Opcode Uses

func (op ConvertCategory) Opcode() RegRegTypeSf

type DataProcessing2 Uses

type DataProcessing2 uint8

Data-processing (2 source) instruction's "opcode" field

func (DataProcessing2) OpcodeReg Uses

func (op DataProcessing2) OpcodeReg() RegRegRegSf

type DiscardRegRegType Uses

type DiscardRegRegType uint32

func (DiscardRegRegType) RnRm Uses

func (op DiscardRegRegType) RnRm(rn, rm reg.R, t wa.Size) uint32

type Ext Uses

type Ext uint32

func SizeSignExt Uses

func SizeSignExt(t wa.Size) Ext

func SizeZeroExt Uses

func SizeZeroExt(t wa.Size) Ext

type Imm16 Uses

type Imm16 uint32

func (Imm16) I16 Uses

func (op Imm16) I16(imm uint32) uint32

type Imm26 Uses

type Imm26 uint32

func (Imm26) I26 Uses

func (op Imm26) I26(imm uint32) uint32

type Logic Uses

type Logic uint8

Logical instruction's "opc" field

func (Logic) OpcodeImm Uses

func (op Logic) OpcodeImm() RegRegImm6Imm6NSf

func (Logic) OpcodeReg Uses

func (op Logic) OpcodeReg() RegRegImm6RegShiftSf

type Memory Uses

type Memory uint16

Load/store instruction's most significant half-word excluding bit 24 (and 21)

func (Memory) OpcodeReg Uses

func (op Memory) OpcodeReg() RegRegSOptionReg

func (Memory) OpcodeUnscaled Uses

func (op Memory) OpcodeUnscaled() RegRegImm9

type Reg Uses

type Reg uint32

func (Reg) Rn Uses

func (op Reg) Rn(rn reg.R) uint32

type RegImm14Bit Uses

type RegImm14Bit uint32

func (RegImm14Bit) RtI14Bit Uses

func (op RegImm14Bit) RtI14Bit(rt reg.R, imm, bit uint32) uint32

type RegImm16HwSf Uses

type RegImm16HwSf uint32

func (RegImm16HwSf) RdI16Hw Uses

func (op RegImm16HwSf) RdI16Hw(rd reg.R, imm, hw uint32, t wa.Size) uint32

type RegImm19Imm2 Uses

type RegImm19Imm2 uint32

func (RegImm19Imm2) RdI19hiI2lo Uses

func (op RegImm19Imm2) RdI19hiI2lo(r reg.R, hi, lo uint32) uint32

type RegImm19Size Uses

type RegImm19Size uint32

func (RegImm19Size) RtI19 Uses

func (op RegImm19Size) RtI19(r reg.R, imm uint32, t wa.Size) uint32

type RegRegCondRegSf Uses

type RegRegCondRegSf uint32

func (RegRegCondRegSf) RdRnCondRm Uses

func (op RegRegCondRegSf) RdRnCondRm(rd, rn reg.R, cond Cond, rm reg.R, t wa.Size) uint32

type RegRegCondRegType Uses

type RegRegCondRegType uint32

func (RegRegCondRegType) RdRnCondRm Uses

func (op RegRegCondRegType) RdRnCondRm(rd, rn reg.R, cond Cond, rm reg.R, t wa.Size) uint32

type RegRegImm12ShiftSf Uses

type RegRegImm12ShiftSf uint32

func (RegRegImm12ShiftSf) RdRnI12S2 Uses

func (op RegRegImm12ShiftSf) RdRnI12S2(rd, rn reg.R, imm, shift uint32, t wa.Size) uint32

type RegRegImm12Size Uses

type RegRegImm12Size uint32

func (RegRegImm12Size) RdRnI12 Uses

func (op RegRegImm12Size) RdRnI12(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegImm3ExtRegSf Uses

type RegRegImm3ExtRegSf uint32

func (RegRegImm3ExtRegSf) RdRnI3ExtRm Uses

func (op RegRegImm3ExtRegSf) RdRnI3ExtRm(rd, rn reg.R, imm uint32, option Ext, rm reg.R, t wa.Size) uint32

type RegRegImm6Imm6NSf Uses

type RegRegImm6Imm6NSf uint32

func (RegRegImm6Imm6NSf) RdRnI6sI6r Uses

func (op RegRegImm6Imm6NSf) RdRnI6sI6r(rd, rn reg.R, imms, immr uint32, t wa.Size) uint32

type RegRegImm6RegShiftSf Uses

type RegRegImm6RegShiftSf uint32

func (RegRegImm6RegShiftSf) RdRnI6RmS2 Uses

func (op RegRegImm6RegShiftSf) RdRnI6RmS2(rd, rn reg.R, imm uint32, rm reg.R, shift Shift, t wa.Size) uint32

type RegRegImm9 Uses

type RegRegImm9 uint32

func (RegRegImm9) RtRnI9 Uses

func (op RegRegImm9) RtRnI9(rt, rn reg.R, imm uint32) uint32

type RegRegImm9Size Uses

type RegRegImm9Size uint32

func (RegRegImm9Size) RtRnI9 Uses

func (op RegRegImm9Size) RtRnI9(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegRegRegSf Uses

type RegRegRegRegSf uint32

func (RegRegRegRegSf) RdRnRaRm Uses

func (op RegRegRegRegSf) RdRnRaRm(rd, rn, ra, rm reg.R, t wa.Size) uint32

type RegRegRegSf Uses

type RegRegRegSf uint32

func (RegRegRegSf) RdRnRm Uses

func (op RegRegRegSf) RdRnRm(rd, rn, rm reg.R, t wa.Size) uint32

type RegRegRegType Uses

type RegRegRegType uint32

func (RegRegRegType) RdRnRm Uses

func (op RegRegRegType) RdRnRm(rd, rn, rm reg.R, t wa.Size) uint32

type RegRegSOptionReg Uses

type RegRegSOptionReg uint32

func (RegRegSOptionReg) RtRnSOptionRm Uses

func (op RegRegSOptionReg) RtRnSOptionRm(rt, rn reg.R, s S, option Ext, rm reg.R) uint32

type RegRegSOptionRegSize Uses

type RegRegSOptionRegSize uint32

func (RegRegSOptionRegSize) RtRnSOptionRm Uses

func (op RegRegSOptionRegSize) RtRnSOptionRm(rt, rn reg.R, s S, option Ext, rm reg.R, t wa.Type) uint32

type RegRegSf Uses

type RegRegSf uint32

func (RegRegSf) RdRn Uses

func (op RegRegSf) RdRn(rd, rn reg.R, t wa.Size) uint32

type RegRegType Uses

type RegRegType uint32

func (RegRegType) RdRn Uses

func (op RegRegType) RdRn(rd, rn reg.R, t wa.Size) uint32

type RegRegTypeSf Uses

type RegRegTypeSf uint32

func (RegRegTypeSf) RdRn Uses

func (op RegRegTypeSf) RdRn(rd, rn reg.R, floatType, intType wa.Size) uint32

type S Uses

type S uint32

type Shift Uses

type Shift uint32

type SystemReg Uses

type SystemReg uint32

func (SystemReg) Rt Uses

func (op SystemReg) Rt(rt reg.R) uint32

type UnaryFloat Uses

type UnaryFloat uint8

Floating-point (1 source) instruction's bits 15-20

func (UnaryFloat) Opcode Uses

func (op UnaryFloat) Opcode() RegRegType

Package in imports 3 packages (graph) and is imported by 1 packages. Updated 2020-09-02. Refresh now. Tools for package owners.