Go: cmd/internal/obj/arm64 Index | Files

package arm64

import "cmd/internal/obj/arm64"

Package arm64 implements an ARM64 assembler. Go assembly syntax is different from GNU ARM64 syntax, but we can still follow the general rules to map between them.

Instructions mnemonics mapping rules

1. Most instructions use width suffixes of instruction names to indicate operand width rather than using different register names.

Examples:
  ADC R24, R14, R12          <=>     adc x12, x24
  ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
  FCMPS F2, F3               <=>     fcmp s3, s2
  FCMPD F2, F3               <=>     fcmp d3, d2
  FCVTDH F2, F3              <=>     fcvt h3, d2

2. Go uses .P and .W suffixes to indicate post-increment and pre-increment.

Examples:
  MOVD.P -8(R10), R8         <=>      ldr x8, [x10],#-8
  MOVB.W 16(R16), R10        <=>      ldrsb x10, [x16,#16]!
  MOVBU.W 16(R16), R10       <=>      ldrb x10, [x16,#16]!

3. Go uses a series of MOV instructions as load and store.

64-bit variant ldr, str, stur => MOVD; 32-bit variant str, stur, ldrsw => MOVW; 32-bit variant ldr => MOVWU; ldrb => MOVBU; ldrh => MOVHU; ldrsb, sturb, strb => MOVB; ldrsh, sturh, strh => MOVH.

4. Go moves conditions into opcode suffix, like BLT.

5. Go adds a V prefix for most floating-point and SIMD instructions, except cryptographic extension instructions and floating-point(scalar) instructions.

Examples:
  VADD V5.H8, V18.H8, V9.H8         <=>      add v9.8h, v18.8h, v5.8h
  VLD1.P (R6)(R11), [V31.D1]        <=>      ld1 {v31.1d}, [x6], x11
  VFMLA V29.S2, V20.S2, V14.S2      <=>      fmla v14.2s, v20.2s, v29.2s
  AESD V22.B16, V19.B16             <=>      aesd v19.16b, v22.16b
  SCVTFWS R3, F16                   <=>      scvtf s17, w6

6. Align directive

Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned to a specified boundary by padding with NOOP instruction. The alignment value supported on arm64 must be a power of 2 and in the range of [8, 2048].

Examples:
  PCALIGN $16
  MOVD $2, R0          // This instruction is aligned with 16 bytes.
  PCALIGN $1024
  MOVD $3, R1          // This instruction is aligned with 1024 bytes.

PCALIGN also changes the function alignment. If a function has one or more PCALIGN directives, its address will be aligned to the same or coarser boundary, which is the maximum of all the alignment values.

In the following example, the function Add is aligned with 128 bytes.

Examples:
  TEXT ·Add(SB),$40-16
  MOVD $2, R0
  PCALIGN $32
  MOVD $4, R1
  PCALIGN $128
  MOVD $8, R2
  RET

On arm64, functions in Go are aligned to 16 bytes by default, we can also use PCALGIN to set the function alignment. The functions that need to be aligned are preferably using NOFRAME and NOSPLIT to avoid the impact of the prologues inserted by the assembler, so that the function address will have the same alignment as the first hand-written instruction.

In the following example, PCALIGN at the entry of the function Add will align its address to 2048 bytes.

Examples:
  TEXT ·Add(SB),NOSPLIT|NOFRAME,$0
    PCALIGN $2048
    MOVD $1, R0
    MOVD $1, R1
    RET

Special Cases.

(1) umov is written as VMOV.

(2) br is renamed JMP, blr is renamed CALL.

(3) No need to add "W" suffix: LDARB, LDARH, LDAXRB, LDAXRH, LDTRH, LDXRB, LDXRH.

(4) In Go assembly syntax, NOP is a zero-width pseudo-instruction serves generic purpose, nothing related to real ARM64 instruction. NOOP serves for the hardware nop instruction. NOOP is an alias of HINT $0.

Examples:
  VMOV V13.B[1], R20      <=>      mov x20, v13.b[1]
  VMOV V13.H[1], R20      <=>      mov w20, v13.h[1]
  JMP (R3)                <=>      br x3
  CALL (R17)              <=>      blr x17
  LDAXRB (R19), R16       <=>      ldaxrb w16, [x19]
  NOOP                    <=>      nop

Register mapping rules

1. All basic register names are written as Rn.

2. Go uses ZR as the zero register and RSP as the stack pointer.

3. Bn, Hn, Dn, Sn and Qn instructions are written as Fn in floating-point instructions and as Vn in SIMD instructions.

Argument mapping rules

1. The operands appear in left-to-right assignment order.

Go reverses the arguments of most instructions.

Examples:
  ADD R11.SXTB<<1, RSP, R25      <=>      add x25, sp, w11, sxtb #1
  VADD V16, V19, V14             <=>      add d14, d19, d16

Special Cases.

(1) Argument order is the same as in the GNU ARM64 syntax: cbz, cbnz and some store instructions, such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1.

Examples:
  MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
  MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
  STLRH R21, (R19)      <=>    stlrh w21, [x19]

(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>

Examples:
  MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
  SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3

(3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>

Examples:
  FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
  FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:
  BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
  UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

(5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>

Examples:
  FCCMPD AL, F8, F26, $0     <=>    fccmp d26, d8, #0x0, al
  FCCMPS VS, F29, F4, $4     <=>    fccmp s4, s29, #0x4, vs
  FCCMPED LE, F20, F5, $13   <=>    fccmpe d5, d20, #0xd, le
  FCCMPES NE, F26, F10, $0   <=>    fccmpe s10, s26, #0x0, ne

(6) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, $<imm>, $<nzcv>

Examples:
  CCMP MI, R22, $12, $13     <=>    ccmp x22, #0xc, #0xd, mi
  CCMNW AL, R1, $11, $8      <=>    ccmn w1, #0xb, #0x8, al

(7) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, <Rm>, $<nzcv>

Examples:
  CCMN VS, R13, R22, $10     <=>    ccmn x13, x22, #0xa, vs
  CCMPW HS, R19, R14, $11    <=>    ccmp w19, w14, #0xb, cs

(9) CSEL, CSELW, CSNEG, CSNEGW, CSINC, CSINCW <cond>, <Rn>, <Rm>, <Rd> ; FCSELD, FCSELS <cond>, <Fn>, <Fm>, <Fd>

Examples:
  CSEL GT, R0, R19, R1        <=>    csel x1, x0, x19, gt
  CSNEGW GT, R7, R17, R8      <=>    csneg w8, w7, w17, gt
  FCSELD EQ, F15, F18, F16    <=>    fcsel d16, d15, d18, eq

(10) TBNZ, TBZ $<imm>, <Rt>, <label>

(11) STLXR, STLXRW, STXR, STXRW, STLXRB, STLXRH, STXRB, STXRH <Rf>, (<Rn|RSP>), <Rs>

Examples:
  STLXR ZR, (R15), R16    <=>    stlxr w16, xzr, [x15]
  STXRB R9, (R21), R19    <=>    stxrb w19, w9, [x21]

(12) STLXP, STLXPW, STXP, STXPW (<Rf1>, <Rf2>), (<Rn|RSP>), <Rs>

Examples:
  STLXP (R17, R19), (R4), R5      <=>    stlxp w5, x17, x19, [x4]
  STXPW (R30, R25), (R22), R13    <=>    stxp w13, w30, w25, [x22]

2. Expressions for special arguments.

#<immediate> is written as $<immediate>.

Optionally-shifted immediate.

Examples:
  ADD $(3151<<12), R14, R20     <=>    add x20, x14, #0xc4f, lsl #12
  ADDW $1864, R25, R6           <=>    add w6, w25, #0x748

Optionally-shifted registers are written as <Rm>{<shift><amount>}. The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).

Examples:
  ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
  ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}. <extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

Examples:
  ADDS R19.UXTB<<4, R9, R26     <=>    adds x26, x9, w19, uxtb #4
  ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx

Memory references: [<Xn|SP>{,#0}] is written as (Rn|RSP), a base register and an immediate offset is written as imm(Rn|RSP), a base register and an offset register is written as (Rn|RSP)(Rm).

Examples:
  LDAR (R22), R9                  <=>    ldar x9, [x22]
  LDP 28(R17), (R15, R23)         <=>    ldp x15, x23, [x17,#28]
  MOVWU (R4)(R12<<2), R8          <=>    ldr w8, [x4, x12, lsl #2]
  MOVD (R7)(R11.UXTW<<3), R25     <=>    ldr x25, [x7,w11,uxtw #3]
  MOVBU (R27)(R23), R14           <=>    ldrb w14, [x27,x23]

Register pairs are written as (Rt1, Rt2).

Examples:
  LDP.P -240(R11), (R12, R26)    <=>    ldp x12, x26, [x11],#-240

Register with arrangement and register with arrangement and index.

Examples:
  VADD V5.H8, V18.H8, V9.H8                     <=>    add v9.8h, v18.8h, v5.8h
  VLD1 (R2), [V21.B16]                          <=>    ld1 {v21.16b}, [x2]
  VST1.P V9.S[1], (R16)(R21)                    <=>    st1 {v9.s}[1], [x16], x28
  VST1.P [V13.H8, V14.H8, V15.H8], (R3)(R14)    <=>    st1 {v13.8h-v15.8h}, [x3], x14
  VST1.P [V14.D1, V15.D1], (R7)(R23)            <=>    st1 {v14.1d, v15.1d}, [x7], x23

Index

Package Files

a.out.go anames.go anames7.go asm7.go doc.go list7.go obj7.go sysRegEnc.go

Constants

const (
    NSNAME = 8
    NSYM   = 50
    NREG   = 32 /* number of general registers */
    NFREG  = 32 /* number of floating point registers */
)
const (
    // integer
    REG_R0 = obj.RBaseARM64 + iota
    REG_R1
    REG_R2
    REG_R3
    REG_R4
    REG_R5
    REG_R6
    REG_R7
    REG_R8
    REG_R9
    REG_R10
    REG_R11
    REG_R12
    REG_R13
    REG_R14
    REG_R15
    REG_R16
    REG_R17
    REG_R18
    REG_R19
    REG_R20
    REG_R21
    REG_R22
    REG_R23
    REG_R24
    REG_R25
    REG_R26
    REG_R27
    REG_R28
    REG_R29
    REG_R30
    REG_R31

    // scalar floating point
    REG_F0
    REG_F1
    REG_F2
    REG_F3
    REG_F4
    REG_F5
    REG_F6
    REG_F7
    REG_F8
    REG_F9
    REG_F10
    REG_F11
    REG_F12
    REG_F13
    REG_F14
    REG_F15
    REG_F16
    REG_F17
    REG_F18
    REG_F19
    REG_F20
    REG_F21
    REG_F22
    REG_F23
    REG_F24
    REG_F25
    REG_F26
    REG_F27
    REG_F28
    REG_F29
    REG_F30
    REG_F31

    // SIMD
    REG_V0
    REG_V1
    REG_V2
    REG_V3
    REG_V4
    REG_V5
    REG_V6
    REG_V7
    REG_V8
    REG_V9
    REG_V10
    REG_V11
    REG_V12
    REG_V13
    REG_V14
    REG_V15
    REG_V16
    REG_V17
    REG_V18
    REG_V19
    REG_V20
    REG_V21
    REG_V22
    REG_V23
    REG_V24
    REG_V25
    REG_V26
    REG_V27
    REG_V28
    REG_V29
    REG_V30
    REG_V31

    // The EQ in
    // 	CSET	EQ, R0
    // is encoded as TYPE_REG, even though it's not really a register.
    COND_EQ
    COND_NE
    COND_HS
    COND_LO
    COND_MI
    COND_PL
    COND_VS
    COND_VC
    COND_HI
    COND_LS
    COND_GE
    COND_LT
    COND_GT
    COND_LE
    COND_AL
    COND_NV

    REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
)

General purpose registers, kept in the low bits of Prog.Reg.

const (
    REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
    REG_ELEM                                    // Vn.<T>[index]
    REG_ELEM_END
)

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement: <T>

const (
    REG_UXTB = REG_EXT + iota<<8
    REG_UXTH
    REG_UXTW
    REG_UXTX
    REG_SXTB
    REG_SXTH
    REG_SXTW
    REG_SXTX
)
const (
    REG_SPECIAL = obj.RBaseARM64 + 1<<12
    REG_DAIFSet = SYSREG_END + iota
    REG_DAIFClr
    REG_PLDL1KEEP
    REG_PLDL1STRM
    REG_PLDL2KEEP
    REG_PLDL2STRM
    REG_PLDL3KEEP
    REG_PLDL3STRM
    REG_PLIL1KEEP
    REG_PLIL1STRM
    REG_PLIL2KEEP
    REG_PLIL2STRM
    REG_PLIL3KEEP
    REG_PLIL3STRM
    REG_PSTL1KEEP
    REG_PSTL1STRM
    REG_PSTL2KEEP
    REG_PSTL2STRM
    REG_PSTL3KEEP
    REG_PSTL3STRM
)

Special registers, after subtracting obj.RBaseARM64, bit 12 indicates a special register and the low bits select the register. SYSREG_END is the last item in the automatically generated system register declaration, and it is defined in the sysRegEnc.go file.

const (
    REGMIN = REG_R7  // register variables allocated from here to REGMAX
    REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
    REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
    REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
    REGMAX = REG_R25

    REGCTXT = REG_R26 // environment for closures
    REGTMP  = REG_R27 // reserved for liblink
    REGG    = REG_R28 // G
    REGFP   = REG_R29 // frame pointer, unused in the Go toolchain
    REGLINK = REG_R30

    // ARM64 uses R31 as both stack pointer and zero register,
    // depending on the instruction. To differentiate RSP from ZR,
    // we use a different numeric value for REGZERO and REGSP.
    REGZERO = REG_R31
    REGSP   = REG_RSP

    FREGRET = REG_F0
    FREGMIN = REG_F7  // first register variable
    FREGMAX = REG_F26 // last register variable for 7g only
    FREGEXT = REG_F26 // first external register
)

Register assignments:

compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down

compiler allocates register variables F7-F26 compiler allocates external registers F26 down

const (
    /* mark flags */
    LABEL = 1 << iota
    LEAF
    FLOAT
    BRANCH
    LOAD
    FCMP
    SYNC
    LIST
    FOLL
    NOSCHED
)
const (
    // optab is sorted based on the order of these constants
    // and the first match is chosen.
    // The more specific class needs to come earlier.
    C_NONE   = iota
    C_REG    // R0..R30
    C_RSP    // R0..R30, RSP
    C_FREG   // F0..F31
    C_VREG   // V0..V31
    C_PAIR   // (Rn, Rm)
    C_SHIFT  // Rn<<2
    C_EXTREG // Rn.UXTB[<<3]
    C_SPR    // REG_NZCV
    C_COND   // EQ, NE, etc
    C_ARNG   // Vn.<T>
    C_ELEM   // Vn.<T>[index]
    C_LIST   // [V1, V2, V3]

    C_ZCON     // $0 or ZR
    C_ABCON0   // could be C_ADDCON0 or C_BITCON
    C_ADDCON0  // 12-bit unsigned, unshifted
    C_ABCON    // could be C_ADDCON or C_BITCON
    C_AMCON    // could be C_ADDCON or C_MOVCON
    C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
    C_MBCON    // could be C_MOVCON or C_BITCON
    C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
    C_BITCON   // bitfield and logical immediate masks
    C_ADDCON2  // 24-bit constant
    C_LCON     // 32-bit constant
    C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
    C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
    C_VCON     // 64-bit constant
    C_FCON     // floating-point constant
    C_VCONADDR // 64-bit memory address

    C_AACON // ADDCON offset in auto constant $a(FP)
    C_LACON // 32-bit offset in auto constant $a(FP)
    C_AECON // ADDCON offset in extern constant $e(SB)

    // TODO(aram): only one branch class should be enough
    C_SBRA // for TYPE_BRANCH
    C_LBRA

    C_ZAUTO      // 0(RSP)
    C_NSAUTO_8   // -256 <= x < 0, 0 mod 8
    C_NSAUTO_4   // -256 <= x < 0, 0 mod 4
    C_NSAUTO     // -256 <= x < 0
    C_NPAUTO     // -512 <= x < 0, 0 mod 8
    C_NAUTO4K    // -4095 <= x < 0
    C_PSAUTO_8   // 0 to 255, 0 mod 8
    C_PSAUTO_4   // 0 to 255, 0 mod 4
    C_PSAUTO     // 0 to 255
    C_PPAUTO     // 0 to 504, 0 mod 8
    C_UAUTO4K_8  // 0 to 4095, 0 mod 8
    C_UAUTO4K_4  // 0 to 4095, 0 mod 4
    C_UAUTO4K_2  // 0 to 4095, 0 mod 2
    C_UAUTO4K    // 0 to 4095
    C_UAUTO8K_8  // 0 to 8190, 0 mod 8
    C_UAUTO8K_4  // 0 to 8190, 0 mod 4
    C_UAUTO8K    // 0 to 8190, 0 mod 2
    C_UAUTO16K_8 // 0 to 16380, 0 mod 8
    C_UAUTO16K   // 0 to 16380, 0 mod 4
    C_UAUTO32K   // 0 to 32760, 0 mod 8
    C_LAUTO      // any other 32-bit constant

    C_SEXT1  // 0 to 4095, direct
    C_SEXT2  // 0 to 8190
    C_SEXT4  // 0 to 16380
    C_SEXT8  // 0 to 32760
    C_SEXT16 // 0 to 65520
    C_LEXT

    C_ZOREG    // 0(R)
    C_NSOREG_8 // must mirror C_NSAUTO_8, etc
    C_NSOREG_4
    C_NSOREG
    C_NPOREG
    C_NOREG4K
    C_PSOREG_8
    C_PSOREG_4
    C_PSOREG
    C_PPOREG
    C_UOREG4K_8
    C_UOREG4K_4
    C_UOREG4K_2
    C_UOREG4K
    C_UOREG8K_8
    C_UOREG8K_4
    C_UOREG8K
    C_UOREG16K_8
    C_UOREG16K
    C_UOREG32K
    C_LOREG

    C_ADDR // TODO(aram): explain difference from C_VCONADDR

    // The GOT slot for a symbol in -dynlink mode.
    C_GOTADDR

    // TLS "var" in local exec mode: will become a constant offset from
    // thread local base that is ultimately chosen by the program linker.
    C_TLS_LE

    // TLS "var" in initial exec mode: will become a memory address (chosen
    // by the program linker) that the dynamic linker will fill with the
    // offset from the thread local base.
    C_TLS_IE

    C_ROFF // register offset (including register extended)

    C_GOK
    C_TEXTSIZE
    C_NCLASS // must be last
)
const (
    C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
    C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
)
const (
    AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
    AADCS
    AADCSW
    AADCW
    AADD
    AADDS
    AADDSW
    AADDW
    AADR
    AADRP
    AAND
    AANDS
    AANDSW
    AANDW
    AASR
    AASRW
    AAT
    ABFI
    ABFIW
    ABFM
    ABFMW
    ABFXIL
    ABFXILW
    ABIC
    ABICS
    ABICSW
    ABICW
    ABRK
    ACBNZ
    ACBNZW
    ACBZ
    ACBZW
    ACCMN
    ACCMNW
    ACCMP
    ACCMPW
    ACINC
    ACINCW
    ACINV
    ACINVW
    ACLREX
    ACLS
    ACLSW
    ACLZ
    ACLZW
    ACMN
    ACMNW
    ACMP
    ACMPW
    ACNEG
    ACNEGW
    ACRC32B
    ACRC32CB
    ACRC32CH
    ACRC32CW
    ACRC32CX
    ACRC32H
    ACRC32W
    ACRC32X
    ACSEL
    ACSELW
    ACSET
    ACSETM
    ACSETMW
    ACSETW
    ACSINC
    ACSINCW
    ACSINV
    ACSINVW
    ACSNEG
    ACSNEGW
    ADC
    ADCPS1
    ADCPS2
    ADCPS3
    ADMB
    ADRPS
    ADSB
    AEON
    AEONW
    AEOR
    AEORW
    AERET
    AEXTR
    AEXTRW
    AHINT
    AHLT
    AHVC
    AIC
    AISB
    ALDADDAB
    ALDADDAD
    ALDADDAH
    ALDADDAW
    ALDADDALB
    ALDADDALD
    ALDADDALH
    ALDADDALW
    ALDADDB
    ALDADDD
    ALDADDH
    ALDADDW
    ALDADDLB
    ALDADDLD
    ALDADDLH
    ALDADDLW
    ALDANDAB
    ALDANDAD
    ALDANDAH
    ALDANDAW
    ALDANDALB
    ALDANDALD
    ALDANDALH
    ALDANDALW
    ALDANDB
    ALDANDD
    ALDANDH
    ALDANDW
    ALDANDLB
    ALDANDLD
    ALDANDLH
    ALDANDLW
    ALDAR
    ALDARB
    ALDARH
    ALDARW
    ALDAXP
    ALDAXPW
    ALDAXR
    ALDAXRB
    ALDAXRH
    ALDAXRW
    ALDEORAB
    ALDEORAD
    ALDEORAH
    ALDEORAW
    ALDEORALB
    ALDEORALD
    ALDEORALH
    ALDEORALW
    ALDEORB
    ALDEORD
    ALDEORH
    ALDEORW
    ALDEORLB
    ALDEORLD
    ALDEORLH
    ALDEORLW
    ALDORAB
    ALDORAD
    ALDORAH
    ALDORAW
    ALDORALB
    ALDORALD
    ALDORALH
    ALDORALW
    ALDORB
    ALDORD
    ALDORH
    ALDORW
    ALDORLB
    ALDORLD
    ALDORLH
    ALDORLW
    ALDP
    ALDPW
    ALDPSW
    ALDXR
    ALDXRB
    ALDXRH
    ALDXRW
    ALDXP
    ALDXPW
    ALSL
    ALSLW
    ALSR
    ALSRW
    AMADD
    AMADDW
    AMNEG
    AMNEGW
    AMOVK
    AMOVKW
    AMOVN
    AMOVNW
    AMOVZ
    AMOVZW
    AMRS
    AMSR
    AMSUB
    AMSUBW
    AMUL
    AMULW
    AMVN
    AMVNW
    ANEG
    ANEGS
    ANEGSW
    ANEGW
    ANGC
    ANGCS
    ANGCSW
    ANGCW
    ANOOP
    AORN
    AORNW
    AORR
    AORRW
    APRFM
    APRFUM
    ARBIT
    ARBITW
    AREM
    AREMW
    AREV
    AREV16
    AREV16W
    AREV32
    AREVW
    AROR
    ARORW
    ASBC
    ASBCS
    ASBCSW
    ASBCW
    ASBFIZ
    ASBFIZW
    ASBFM
    ASBFMW
    ASBFX
    ASBFXW
    ASDIV
    ASDIVW
    ASEV
    ASEVL
    ASMADDL
    ASMC
    ASMNEGL
    ASMSUBL
    ASMULH
    ASMULL
    ASTXR
    ASTXRB
    ASTXRH
    ASTXP
    ASTXPW
    ASTXRW
    ASTLP
    ASTLPW
    ASTLR
    ASTLRB
    ASTLRH
    ASTLRW
    ASTLXP
    ASTLXPW
    ASTLXR
    ASTLXRB
    ASTLXRH
    ASTLXRW
    ASTP
    ASTPW
    ASUB
    ASUBS
    ASUBSW
    ASUBW
    ASVC
    ASXTB
    ASXTBW
    ASXTH
    ASXTHW
    ASXTW
    ASYS
    ASYSL
    ATBNZ
    ATBZ
    ATLBI
    ATST
    ATSTW
    AUBFIZ
    AUBFIZW
    AUBFM
    AUBFMW
    AUBFX
    AUBFXW
    AUDIV
    AUDIVW
    AUMADDL
    AUMNEGL
    AUMSUBL
    AUMULH
    AUMULL
    AUREM
    AUREMW
    AUXTB
    AUXTH
    AUXTW
    AUXTBW
    AUXTHW
    AWFE
    AWFI
    AYIELD
    AMOVB
    AMOVBU
    AMOVH
    AMOVHU
    AMOVW
    AMOVWU
    AMOVD
    AMOVNP
    AMOVNPW
    AMOVP
    AMOVPD
    AMOVPQ
    AMOVPS
    AMOVPSW
    AMOVPW
    ASWPAD
    ASWPAW
    ASWPAH
    ASWPAB
    ASWPALD
    ASWPALW
    ASWPALH
    ASWPALB
    ASWPD
    ASWPW
    ASWPH
    ASWPB
    ASWPLD
    ASWPLW
    ASWPLH
    ASWPLB
    ABEQ
    ABNE
    ABCS
    ABHS
    ABCC
    ABLO
    ABMI
    ABPL
    ABVS
    ABVC
    ABHI
    ABLS
    ABGE
    ABLT
    ABGT
    ABLE
    AFABSD
    AFABSS
    AFADDD
    AFADDS
    AFCCMPD
    AFCCMPED
    AFCCMPS
    AFCCMPES
    AFCMPD
    AFCMPED
    AFCMPES
    AFCMPS
    AFCVTSD
    AFCVTDS
    AFCVTZSD
    AFCVTZSDW
    AFCVTZSS
    AFCVTZSSW
    AFCVTZUD
    AFCVTZUDW
    AFCVTZUS
    AFCVTZUSW
    AFDIVD
    AFDIVS
    AFLDPD
    AFLDPS
    AFMOVD
    AFMOVS
    AFMULD
    AFMULS
    AFNEGD
    AFNEGS
    AFSQRTD
    AFSQRTS
    AFSTPD
    AFSTPS
    AFSUBD
    AFSUBS
    ASCVTFD
    ASCVTFS
    ASCVTFWD
    ASCVTFWS
    AUCVTFD
    AUCVTFS
    AUCVTFWD
    AUCVTFWS
    AWORD
    ADWORD
    AFCSELS
    AFCSELD
    AFMAXS
    AFMINS
    AFMAXD
    AFMIND
    AFMAXNMS
    AFMAXNMD
    AFNMULS
    AFNMULD
    AFRINTNS
    AFRINTND
    AFRINTPS
    AFRINTPD
    AFRINTMS
    AFRINTMD
    AFRINTZS
    AFRINTZD
    AFRINTAS
    AFRINTAD
    AFRINTXS
    AFRINTXD
    AFRINTIS
    AFRINTID
    AFMADDS
    AFMADDD
    AFMSUBS
    AFMSUBD
    AFNMADDS
    AFNMADDD
    AFNMSUBS
    AFNMSUBD
    AFMINNMS
    AFMINNMD
    AFCVTDH
    AFCVTHS
    AFCVTHD
    AFCVTSH
    AAESD
    AAESE
    AAESIMC
    AAESMC
    ASHA1C
    ASHA1H
    ASHA1M
    ASHA1P
    ASHA1SU0
    ASHA1SU1
    ASHA256H
    ASHA256H2
    ASHA256SU0
    ASHA256SU1
    AVADD
    AVADDP
    AVAND
    AVCMEQ
    AVCNT
    AVEOR
    AVMOV
    AVLD1
    AVLD2
    AVLD3
    AVLD4
    AVLD1R
    AVLD2R
    AVLD3R
    AVLD4R
    AVORR
    AVREV16
    AVREV32
    AVREV64
    AVST1
    AVST2
    AVST3
    AVST4
    AVDUP
    AVADDV
    AVMOVI
    AVUADDLV
    AVSUB
    AVFMLA
    AVFMLS
    AVPMULL
    AVPMULL2
    AVEXT
    AVRBIT
    AVUSHR
    AVSHL
    AVSRI
    AVTBL
    AVZIP1
    AVZIP2
    ALAST
    AB  = obj.AJMP
    ABL = obj.ACALL
)
const (
    // shift types
    SHIFT_LL = 0 << 22
    SHIFT_LR = 1 << 22
    SHIFT_AR = 2 << 22
)
const (
    // arrangement types
    ARNG_8B = iota
    ARNG_16B
    ARNG_1D
    ARNG_4H
    ARNG_8H
    ARNG_2S
    ARNG_4S
    ARNG_2D
    ARNG_1Q
    ARNG_B
    ARNG_H
    ARNG_S
    ARNG_D
)

Arrangement for ARM64 SIMD instructions

const (
    S32     = 0 << 31
    S64     = 1 << 31
    Sbit    = 1 << 29
    LSL0_32 = 2 << 13
    LSL0_64 = 3 << 13
)
const (
    // Optab.flag
    LFROM     = 1 << 0 // p.From uses constant pool
    LTO       = 1 << 1 // p.To uses constant pool
    NOTUSETMP = 1 << 2 // p expands to multiple instructions, but does NOT use REGTMP
)
const (
    SYSREG_BEGIN = REG_SPECIAL + iota
    REG_ACTLR_EL1
    REG_AFSR0_EL1
    REG_AFSR1_EL1
    REG_AIDR_EL1
    REG_AMAIR_EL1
    REG_AMCFGR_EL0
    REG_AMCGCR_EL0
    REG_AMCNTENCLR0_EL0
    REG_AMCNTENCLR1_EL0
    REG_AMCNTENSET0_EL0
    REG_AMCNTENSET1_EL0
    REG_AMCR_EL0
    REG_AMEVCNTR00_EL0
    REG_AMEVCNTR01_EL0
    REG_AMEVCNTR02_EL0
    REG_AMEVCNTR03_EL0
    REG_AMEVCNTR04_EL0
    REG_AMEVCNTR05_EL0
    REG_AMEVCNTR06_EL0
    REG_AMEVCNTR07_EL0
    REG_AMEVCNTR08_EL0
    REG_AMEVCNTR09_EL0
    REG_AMEVCNTR010_EL0
    REG_AMEVCNTR011_EL0
    REG_AMEVCNTR012_EL0
    REG_AMEVCNTR013_EL0
    REG_AMEVCNTR014_EL0
    REG_AMEVCNTR015_EL0
    REG_AMEVCNTR10_EL0
    REG_AMEVCNTR11_EL0
    REG_AMEVCNTR12_EL0
    REG_AMEVCNTR13_EL0
    REG_AMEVCNTR14_EL0
    REG_AMEVCNTR15_EL0
    REG_AMEVCNTR16_EL0
    REG_AMEVCNTR17_EL0
    REG_AMEVCNTR18_EL0
    REG_AMEVCNTR19_EL0
    REG_AMEVCNTR110_EL0
    REG_AMEVCNTR111_EL0
    REG_AMEVCNTR112_EL0
    REG_AMEVCNTR113_EL0
    REG_AMEVCNTR114_EL0
    REG_AMEVCNTR115_EL0
    REG_AMEVTYPER00_EL0
    REG_AMEVTYPER01_EL0
    REG_AMEVTYPER02_EL0
    REG_AMEVTYPER03_EL0
    REG_AMEVTYPER04_EL0
    REG_AMEVTYPER05_EL0
    REG_AMEVTYPER06_EL0
    REG_AMEVTYPER07_EL0
    REG_AMEVTYPER08_EL0
    REG_AMEVTYPER09_EL0
    REG_AMEVTYPER010_EL0
    REG_AMEVTYPER011_EL0
    REG_AMEVTYPER012_EL0
    REG_AMEVTYPER013_EL0
    REG_AMEVTYPER014_EL0
    REG_AMEVTYPER015_EL0
    REG_AMEVTYPER10_EL0
    REG_AMEVTYPER11_EL0
    REG_AMEVTYPER12_EL0
    REG_AMEVTYPER13_EL0
    REG_AMEVTYPER14_EL0
    REG_AMEVTYPER15_EL0
    REG_AMEVTYPER16_EL0
    REG_AMEVTYPER17_EL0
    REG_AMEVTYPER18_EL0
    REG_AMEVTYPER19_EL0
    REG_AMEVTYPER110_EL0
    REG_AMEVTYPER111_EL0
    REG_AMEVTYPER112_EL0
    REG_AMEVTYPER113_EL0
    REG_AMEVTYPER114_EL0
    REG_AMEVTYPER115_EL0
    REG_AMUSERENR_EL0
    REG_APDAKeyHi_EL1
    REG_APDAKeyLo_EL1
    REG_APDBKeyHi_EL1
    REG_APDBKeyLo_EL1
    REG_APGAKeyHi_EL1
    REG_APGAKeyLo_EL1
    REG_APIAKeyHi_EL1
    REG_APIAKeyLo_EL1
    REG_APIBKeyHi_EL1
    REG_APIBKeyLo_EL1
    REG_CCSIDR2_EL1
    REG_CCSIDR_EL1
    REG_CLIDR_EL1
    REG_CNTFRQ_EL0
    REG_CNTKCTL_EL1
    REG_CNTP_CTL_EL0
    REG_CNTP_CVAL_EL0
    REG_CNTP_TVAL_EL0
    REG_CNTPCT_EL0
    REG_CNTPS_CTL_EL1
    REG_CNTPS_CVAL_EL1
    REG_CNTPS_TVAL_EL1
    REG_CNTV_CTL_EL0
    REG_CNTV_CVAL_EL0
    REG_CNTV_TVAL_EL0
    REG_CNTVCT_EL0
    REG_CONTEXTIDR_EL1
    REG_CPACR_EL1
    REG_CSSELR_EL1
    REG_CTR_EL0
    REG_CurrentEL
    REG_DAIF
    REG_DBGAUTHSTATUS_EL1
    REG_DBGBCR0_EL1
    REG_DBGBCR1_EL1
    REG_DBGBCR2_EL1
    REG_DBGBCR3_EL1
    REG_DBGBCR4_EL1
    REG_DBGBCR5_EL1
    REG_DBGBCR6_EL1
    REG_DBGBCR7_EL1
    REG_DBGBCR8_EL1
    REG_DBGBCR9_EL1
    REG_DBGBCR10_EL1
    REG_DBGBCR11_EL1
    REG_DBGBCR12_EL1
    REG_DBGBCR13_EL1
    REG_DBGBCR14_EL1
    REG_DBGBCR15_EL1
    REG_DBGBVR0_EL1
    REG_DBGBVR1_EL1
    REG_DBGBVR2_EL1
    REG_DBGBVR3_EL1
    REG_DBGBVR4_EL1
    REG_DBGBVR5_EL1
    REG_DBGBVR6_EL1
    REG_DBGBVR7_EL1
    REG_DBGBVR8_EL1
    REG_DBGBVR9_EL1
    REG_DBGBVR10_EL1
    REG_DBGBVR11_EL1
    REG_DBGBVR12_EL1
    REG_DBGBVR13_EL1
    REG_DBGBVR14_EL1
    REG_DBGBVR15_EL1
    REG_DBGCLAIMCLR_EL1
    REG_DBGCLAIMSET_EL1
    REG_DBGDTR_EL0
    REG_DBGDTRRX_EL0
    REG_DBGDTRTX_EL0
    REG_DBGPRCR_EL1
    REG_DBGWCR0_EL1
    REG_DBGWCR1_EL1
    REG_DBGWCR2_EL1
    REG_DBGWCR3_EL1
    REG_DBGWCR4_EL1
    REG_DBGWCR5_EL1
    REG_DBGWCR6_EL1
    REG_DBGWCR7_EL1
    REG_DBGWCR8_EL1
    REG_DBGWCR9_EL1
    REG_DBGWCR10_EL1
    REG_DBGWCR11_EL1
    REG_DBGWCR12_EL1
    REG_DBGWCR13_EL1
    REG_DBGWCR14_EL1
    REG_DBGWCR15_EL1
    REG_DBGWVR0_EL1
    REG_DBGWVR1_EL1
    REG_DBGWVR2_EL1
    REG_DBGWVR3_EL1
    REG_DBGWVR4_EL1
    REG_DBGWVR5_EL1
    REG_DBGWVR6_EL1
    REG_DBGWVR7_EL1
    REG_DBGWVR8_EL1
    REG_DBGWVR9_EL1
    REG_DBGWVR10_EL1
    REG_DBGWVR11_EL1
    REG_DBGWVR12_EL1
    REG_DBGWVR13_EL1
    REG_DBGWVR14_EL1
    REG_DBGWVR15_EL1
    REG_DCZID_EL0
    REG_DISR_EL1
    REG_DIT
    REG_DLR_EL0
    REG_DSPSR_EL0
    REG_ELR_EL1
    REG_ERRIDR_EL1
    REG_ERRSELR_EL1
    REG_ERXADDR_EL1
    REG_ERXCTLR_EL1
    REG_ERXFR_EL1
    REG_ERXMISC0_EL1
    REG_ERXMISC1_EL1
    REG_ERXMISC2_EL1
    REG_ERXMISC3_EL1
    REG_ERXPFGCDN_EL1
    REG_ERXPFGCTL_EL1
    REG_ERXPFGF_EL1
    REG_ERXSTATUS_EL1
    REG_ESR_EL1
    REG_FAR_EL1
    REG_FPCR
    REG_FPSR
    REG_GCR_EL1
    REG_GMID_EL1
    REG_ICC_AP0R0_EL1
    REG_ICC_AP0R1_EL1
    REG_ICC_AP0R2_EL1
    REG_ICC_AP0R3_EL1
    REG_ICC_AP1R0_EL1
    REG_ICC_AP1R1_EL1
    REG_ICC_AP1R2_EL1
    REG_ICC_AP1R3_EL1
    REG_ICC_ASGI1R_EL1
    REG_ICC_BPR0_EL1
    REG_ICC_BPR1_EL1
    REG_ICC_CTLR_EL1
    REG_ICC_DIR_EL1
    REG_ICC_EOIR0_EL1
    REG_ICC_EOIR1_EL1
    REG_ICC_HPPIR0_EL1
    REG_ICC_HPPIR1_EL1
    REG_ICC_IAR0_EL1
    REG_ICC_IAR1_EL1
    REG_ICC_IGRPEN0_EL1
    REG_ICC_IGRPEN1_EL1
    REG_ICC_PMR_EL1
    REG_ICC_RPR_EL1
    REG_ICC_SGI0R_EL1
    REG_ICC_SGI1R_EL1
    REG_ICC_SRE_EL1
    REG_ICV_AP0R0_EL1
    REG_ICV_AP0R1_EL1
    REG_ICV_AP0R2_EL1
    REG_ICV_AP0R3_EL1
    REG_ICV_AP1R0_EL1
    REG_ICV_AP1R1_EL1
    REG_ICV_AP1R2_EL1
    REG_ICV_AP1R3_EL1
    REG_ICV_BPR0_EL1
    REG_ICV_BPR1_EL1
    REG_ICV_CTLR_EL1
    REG_ICV_DIR_EL1
    REG_ICV_EOIR0_EL1
    REG_ICV_EOIR1_EL1
    REG_ICV_HPPIR0_EL1
    REG_ICV_HPPIR1_EL1
    REG_ICV_IAR0_EL1
    REG_ICV_IAR1_EL1
    REG_ICV_IGRPEN0_EL1
    REG_ICV_IGRPEN1_EL1
    REG_ICV_PMR_EL1
    REG_ICV_RPR_EL1
    REG_ID_AA64AFR0_EL1
    REG_ID_AA64AFR1_EL1
    REG_ID_AA64DFR0_EL1
    REG_ID_AA64DFR1_EL1
    REG_ID_AA64ISAR0_EL1
    REG_ID_AA64ISAR1_EL1
    REG_ID_AA64MMFR0_EL1
    REG_ID_AA64MMFR1_EL1
    REG_ID_AA64MMFR2_EL1
    REG_ID_AA64PFR0_EL1
    REG_ID_AA64PFR1_EL1
    REG_ID_AA64ZFR0_EL1
    REG_ID_AFR0_EL1
    REG_ID_DFR0_EL1
    REG_ID_ISAR0_EL1
    REG_ID_ISAR1_EL1
    REG_ID_ISAR2_EL1
    REG_ID_ISAR3_EL1
    REG_ID_ISAR4_EL1
    REG_ID_ISAR5_EL1
    REG_ID_ISAR6_EL1
    REG_ID_MMFR0_EL1
    REG_ID_MMFR1_EL1
    REG_ID_MMFR2_EL1
    REG_ID_MMFR3_EL1
    REG_ID_MMFR4_EL1
    REG_ID_PFR0_EL1
    REG_ID_PFR1_EL1
    REG_ID_PFR2_EL1
    REG_ISR_EL1
    REG_LORC_EL1
    REG_LOREA_EL1
    REG_LORID_EL1
    REG_LORN_EL1
    REG_LORSA_EL1
    REG_MAIR_EL1
    REG_MDCCINT_EL1
    REG_MDCCSR_EL0
    REG_MDRAR_EL1
    REG_MDSCR_EL1
    REG_MIDR_EL1
    REG_MPAM0_EL1
    REG_MPAM1_EL1
    REG_MPAMIDR_EL1
    REG_MPIDR_EL1
    REG_MVFR0_EL1
    REG_MVFR1_EL1
    REG_MVFR2_EL1
    REG_NZCV
    REG_OSDLR_EL1
    REG_OSDTRRX_EL1
    REG_OSDTRTX_EL1
    REG_OSECCR_EL1
    REG_OSLAR_EL1
    REG_OSLSR_EL1
    REG_PAN
    REG_PAR_EL1
    REG_PMBIDR_EL1
    REG_PMBLIMITR_EL1
    REG_PMBPTR_EL1
    REG_PMBSR_EL1
    REG_PMCCFILTR_EL0
    REG_PMCCNTR_EL0
    REG_PMCEID0_EL0
    REG_PMCEID1_EL0
    REG_PMCNTENCLR_EL0
    REG_PMCNTENSET_EL0
    REG_PMCR_EL0
    REG_PMEVCNTR0_EL0
    REG_PMEVCNTR1_EL0
    REG_PMEVCNTR2_EL0
    REG_PMEVCNTR3_EL0
    REG_PMEVCNTR4_EL0
    REG_PMEVCNTR5_EL0
    REG_PMEVCNTR6_EL0
    REG_PMEVCNTR7_EL0
    REG_PMEVCNTR8_EL0
    REG_PMEVCNTR9_EL0
    REG_PMEVCNTR10_EL0
    REG_PMEVCNTR11_EL0
    REG_PMEVCNTR12_EL0
    REG_PMEVCNTR13_EL0
    REG_PMEVCNTR14_EL0
    REG_PMEVCNTR15_EL0
    REG_PMEVCNTR16_EL0
    REG_PMEVCNTR17_EL0
    REG_PMEVCNTR18_EL0
    REG_PMEVCNTR19_EL0
    REG_PMEVCNTR20_EL0
    REG_PMEVCNTR21_EL0
    REG_PMEVCNTR22_EL0
    REG_PMEVCNTR23_EL0
    REG_PMEVCNTR24_EL0
    REG_PMEVCNTR25_EL0
    REG_PMEVCNTR26_EL0
    REG_PMEVCNTR27_EL0
    REG_PMEVCNTR28_EL0
    REG_PMEVCNTR29_EL0
    REG_PMEVCNTR30_EL0
    REG_PMEVTYPER0_EL0
    REG_PMEVTYPER1_EL0
    REG_PMEVTYPER2_EL0
    REG_PMEVTYPER3_EL0
    REG_PMEVTYPER4_EL0
    REG_PMEVTYPER5_EL0
    REG_PMEVTYPER6_EL0
    REG_PMEVTYPER7_EL0
    REG_PMEVTYPER8_EL0
    REG_PMEVTYPER9_EL0
    REG_PMEVTYPER10_EL0
    REG_PMEVTYPER11_EL0
    REG_PMEVTYPER12_EL0
    REG_PMEVTYPER13_EL0
    REG_PMEVTYPER14_EL0
    REG_PMEVTYPER15_EL0
    REG_PMEVTYPER16_EL0
    REG_PMEVTYPER17_EL0
    REG_PMEVTYPER18_EL0
    REG_PMEVTYPER19_EL0
    REG_PMEVTYPER20_EL0
    REG_PMEVTYPER21_EL0
    REG_PMEVTYPER22_EL0
    REG_PMEVTYPER23_EL0
    REG_PMEVTYPER24_EL0
    REG_PMEVTYPER25_EL0
    REG_PMEVTYPER26_EL0
    REG_PMEVTYPER27_EL0
    REG_PMEVTYPER28_EL0
    REG_PMEVTYPER29_EL0
    REG_PMEVTYPER30_EL0
    REG_PMINTENCLR_EL1
    REG_PMINTENSET_EL1
    REG_PMMIR_EL1
    REG_PMOVSCLR_EL0
    REG_PMOVSSET_EL0
    REG_PMSCR_EL1
    REG_PMSELR_EL0
    REG_PMSEVFR_EL1
    REG_PMSFCR_EL1
    REG_PMSICR_EL1
    REG_PMSIDR_EL1
    REG_PMSIRR_EL1
    REG_PMSLATFR_EL1
    REG_PMSWINC_EL0
    REG_PMUSERENR_EL0
    REG_PMXEVCNTR_EL0
    REG_PMXEVTYPER_EL0
    REG_REVIDR_EL1
    REG_RGSR_EL1
    REG_RMR_EL1
    REG_RNDR
    REG_RNDRRS
    REG_RVBAR_EL1
    REG_SCTLR_EL1
    REG_SCXTNUM_EL0
    REG_SCXTNUM_EL1
    REG_SP_EL0
    REG_SP_EL1
    REG_SPSel
    REG_SPSR_abt
    REG_SPSR_EL1
    REG_SPSR_fiq
    REG_SPSR_irq
    REG_SPSR_und
    REG_SSBS
    REG_TCO
    REG_TCR_EL1
    REG_TFSR_EL1
    REG_TFSRE0_EL1
    REG_TPIDR_EL0
    REG_TPIDR_EL1
    REG_TPIDRRO_EL0
    REG_TRFCR_EL1
    REG_TTBR0_EL1
    REG_TTBR1_EL1
    REG_UAO
    REG_VBAR_EL1
    REG_ZCR_EL1
    SYSREG_END
)
const (
    SR_READ = 1 << iota
    SR_WRITE
)
const (
    BIG = 2048 - 8
)
const OP_NOOP = 0xd503201f

Used for padinng NOOP instruction

const (
    REGFROM = 1
)
const REG_EXT = obj.RBaseARM64 + 1<<11
const REG_LSL = obj.RBaseARM64 + 1<<9

Not registers, but flags that can be combined with regular register constants to indicate extended register conversion. When checking, you should subtract obj.RBaseARM64 first. From this difference, bit 11 indicates extended register, bits 8-10 select the conversion mode. REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.

Variables

var ARM64DWARFRegisters = map[int16]int16{
    REG_R0:  0,
    REG_R1:  1,
    REG_R2:  2,
    REG_R3:  3,
    REG_R4:  4,
    REG_R5:  5,
    REG_R6:  6,
    REG_R7:  7,
    REG_R8:  8,
    REG_R9:  9,
    REG_R10: 10,
    REG_R11: 11,
    REG_R12: 12,
    REG_R13: 13,
    REG_R14: 14,
    REG_R15: 15,
    REG_R16: 16,
    REG_R17: 17,
    REG_R18: 18,
    REG_R19: 19,
    REG_R20: 20,
    REG_R21: 21,
    REG_R22: 22,
    REG_R23: 23,
    REG_R24: 24,
    REG_R25: 25,
    REG_R26: 26,
    REG_R27: 27,
    REG_R28: 28,
    REG_R29: 29,
    REG_R30: 30,

    REG_F0:  64,
    REG_F1:  65,
    REG_F2:  66,
    REG_F3:  67,
    REG_F4:  68,
    REG_F5:  69,
    REG_F6:  70,
    REG_F7:  71,
    REG_F8:  72,
    REG_F9:  73,
    REG_F10: 74,
    REG_F11: 75,
    REG_F12: 76,
    REG_F13: 77,
    REG_F14: 78,
    REG_F15: 79,
    REG_F16: 80,
    REG_F17: 81,
    REG_F18: 82,
    REG_F19: 83,
    REG_F20: 84,
    REG_F21: 85,
    REG_F22: 86,
    REG_F23: 87,
    REG_F24: 88,
    REG_F25: 89,
    REG_F26: 90,
    REG_F27: 91,
    REG_F28: 92,
    REG_F29: 93,
    REG_F30: 94,
    REG_F31: 95,

    REG_V0:  64,
    REG_V1:  65,
    REG_V2:  66,
    REG_V3:  67,
    REG_V4:  68,
    REG_V5:  69,
    REG_V6:  70,
    REG_V7:  71,
    REG_V8:  72,
    REG_V9:  73,
    REG_V10: 74,
    REG_V11: 75,
    REG_V12: 76,
    REG_V13: 77,
    REG_V14: 78,
    REG_V15: 79,
    REG_V16: 80,
    REG_V17: 81,
    REG_V18: 82,
    REG_V19: 83,
    REG_V20: 84,
    REG_V21: 85,
    REG_V22: 86,
    REG_V23: 87,
    REG_V24: 88,
    REG_V25: 89,
    REG_V26: 90,
    REG_V27: 91,
    REG_V28: 92,
    REG_V29: 93,
    REG_V30: 94,
    REG_V31: 95,
}

http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf

var Anames = []string{ /* 489 elements not displayed */

}
var Linkarm64 = obj.LinkArch{
    Arch:           sys.ArchARM64,
    Init:           buildop,
    Preprocess:     preprocess,
    Assemble:       span7,
    Progedit:       progedit,
    UnaryDst:       unaryDst,
    DWARFRegisters: ARM64DWARFRegisters,
}
var SystemReg = []struct {
    Name string
    Reg  int16
    Enc  uint32

    AccessFlags uint8
}{  /* 431 elements not displayed */

}

func ADR Uses

func ADR(p uint32, o uint32, rt uint32) uint32

func DRconv Uses

func DRconv(a int) string

func FPCCMP Uses

func FPCCMP(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPCMP Uses

func FPCMP(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

func FPCVTI Uses

func FPCVTI(sf uint32, s uint32, type_ uint32, rmode uint32, op uint32) uint32

func FPOP1S Uses

func FPOP1S(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPOP2S Uses

func FPOP2S(m uint32, s uint32, type_ uint32, op uint32) uint32

func FPOP3S Uses

func FPOP3S(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32

func IsAtomicInstruction Uses

func IsAtomicInstruction(as obj.As) bool

func LD2STR Uses

func LD2STR(o uint32) uint32

func LDSTR12U Uses

func LDSTR12U(sz uint32, v uint32, opc uint32) uint32

func LDSTR9S Uses

func LDSTR9S(sz uint32, v uint32, opc uint32) uint32

func LDSTX Uses

func LDSTX(sz uint32, o2 uint32, l uint32, o1 uint32, o0 uint32) uint32

func MOVCONST Uses

func MOVCONST(d int64, s int, rt int) uint32

func OPBIT Uses

func OPBIT(x uint32) uint32

func OPBLR Uses

func OPBLR(x uint32) uint32

func OPBcc Uses

func OPBcc(x uint32) uint32

func OPDP2 Uses

func OPDP2(x uint32) uint32

func OPDP3 Uses

func OPDP3(sf uint32, op54 uint32, op31 uint32, o0 uint32) uint32

func SYSARG4 Uses

func SYSARG4(op1 int, Cn int, Cm int, op2 int) int

func SYSARG5 Uses

func SYSARG5(op0 int, op1 int, Cn int, Cm int, op2 int) int

form offset parameter to SYS; special register number

func SYSHINT Uses

func SYSHINT(x uint32) uint32

func SYSOP Uses

func SYSOP(l uint32, op0 uint32, op1 uint32, crn uint32, crm uint32, op2 uint32, rt uint32) uint32

func SysRegEnc Uses

func SysRegEnc(r int16) (string, uint32, uint8)

type Optab Uses

type Optab struct {
    // contains filtered or unexported fields
}

Package arm64 imports 8 packages (graph) and is imported by 6 packages. Updated 2020-10-14. Refresh now. Tools for package owners.